Compiler-Guided Parallelism Adaption Based on Application Partition for Power-Gated ILP Processor

Tong, Yufeng; Zhang, Wei; Ma, Yung-Cheng; Liu, Yanyan; Yu, Liang; Zhang, Tai; Luo, Haowen

doi:10.1109/tvlsi.2016.2636419

Cited by 3 publications

(4 citation statements)

References 29 publications

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“…Our approach also has significant energy saving at the peak-performance mode. Compared to the previous parallelism control scheme [18] at peak-performance mode, the evaluation reveals a significant room to save energy through parallelism control with performance demand. We recommend developers to do solution space exploration to find a sweet spot between performance and energy cost.…”

Section: Discussionmentioning

confidence: 88%

“…This means that, when pushing the performance demand near peak-performance, an exorbitant energy cost is paid just to gain minuscule saving in execution time. This encourages the application developer to do solution space exploration for PCEO rather than executing in peak-performance mode as in our previous work [18]. Considering all the evaluation results, we recommend the developer to do performance-constrained energy optimization using the region-SRE approach.…”

Section: A Energy Efficiency Of Scaling Parallelismmentioning

confidence: 86%

“…As a result, the amount of cross-slot operand transfers (and hence the energy dissipated on register files) also scales with ILP. Based on the PGRF-VLIW architecture, we further proposed global parallelism adaption heuristic [18] to save energy at peak-performance mode, where each program region is executed with its speedup-saturation parallelism. In this paper, we advance the previous works by taking real-time performance demand to depower more hardware for energy saving.…”

Section: B Related Work: Compiler-directed Leakage Power Controlmentioning

confidence: 99%

“…PCEO raises challenges to parallelism control. The previous work [18] proposes parallelism adaption algorithm to reduce energy consumption at peak-performance mode: each program region is simply assigned its speedup-saturation parallelism. For PCEO, a new algorithm is required to choose parallelism from a set of possible decisions.…”

Section: Introductionmentioning

confidence: 99%

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Compiler-Directed Parallelism Scaling Framework for Performance Constrained Energy Optimization

2020

IEEE Access

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Evolution of semiconductor manufacturing technology leads to the rising trend of leakage current and the end of Dennard scaling. At the dark silicon era, aggressive power gating scheme with quantitative management on power-gated hardware resources is required. This paper proposes a novel approach-parallelism scaling-to control static energy on power-gated parallel hardware. This work presents performance-constrained optimization method to power off the greatest possible amount of hardware. As a first trial, this paper examines the idea on VLIW-style architecture exploiting instruction-level parallelism. This paper establishes a theoretical foundation to realize parallelism scaling. The mathematical programming theory includes (1) topological model to control the granularity of program partitioning, (2) optimal partitioning on well-structured control flow graph in polynomial time, and (3) decision support for parallelism through item packing model guided by energy density. Evaluation conducted on EEMBC Denbench benchmark suite shows at least 15% to 53% saving on static energy compared to non-powergated architecture. Compared to the state-of-art resource management scheme, our approach saves about 20% to 30% energy to meet the same performance demand. The evaluation reveals noteworthy opportunity to save static energy for future dark-silicon architecture design.

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Section: Discussionmentioning

confidence: 88%

Section: A Energy Efficiency Of Scaling Parallelismmentioning

confidence: 86%

Section: B Related Work: Compiler-directed Leakage Power Controlmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Compiler-Directed Parallelism Scaling Framework for Performance Constrained Energy Optimization

2020

IEEE Access

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Heterogeneous Hyperthreading

He,

Liu,

2024

2024 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)

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NeurOMP: Paralelização automática de código utilizando Aprendizagem por Reforço

Saffran¹,

Rocha

Góes

2020

Anais Do XXI Simpósio Em Sistemas Computacionais De Alto Desempenho (SSCAD 2020)

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A criação de aplicações que obtenham o máximo de desempenho computacional nas arquiteturas modernas é uma tarefa complexa. Além de utilizar conhecimentos de paralelismo, o programador precisar ter um amplo conhecimento de vários outros aspectos da aplicação. Por este motivo, os compiladores modernos tentam paralelizar algoritmos de maneira automática, utilizando a análise estática do código. Uma maneira de melhorar o processo de tomada de decisão do compilador é utilizando Aprendizagem por Reforço (RL). Este trabalho propõe e avalia uma otimização, chamada NeurOMP, que utiliza RL para paralelizar for loops em códigos C utilizando a biblioteca OpenMP. Os resultados experimentais mostram que o NeurOMP obtém um speedup médio no CAP Bench de 1.6, similar a um especialista humano.

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Compiler-Guided Parallelism Adaption Based on Application Partition for Power-Gated ILP Processor

Cited by 3 publications

References 29 publications

Compiler-Directed Parallelism Scaling Framework for Performance Constrained Energy Optimization

Compiler-Directed Parallelism Scaling Framework for Performance Constrained Energy Optimization

Heterogeneous Hyperthreading

NeurOMP: Paralelização automática de código utilizando Aprendizagem por Reforço

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