Compiler-Directed Soft Error Mitigation for Embedded Systems

Martínez-Álvarez, Antonio; Cuenca-Asensi, Sergio; Restrepo-Calle, Felipe; Pinto, Francisco Rogelio Palomo; Guzmán-Miranda, H.; Aguirre, M.A.

doi:10.1109/tdsc.2011.54

Cited by 47 publications

(25 citation statements)

References 32 publications

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“…In order to evaluate the proposed technique, firstly, it was implemented using the API (Application Programming Interface) exposed by the Software Hardening Environment (SHE ) (proposed in [47]). Secondly, the fault coverage of the approach was assessed using an FPGA emulation-based fault injection tool called FTUnshades [50].…”

Section: Discussionmentioning

confidence: 99%

“…In this context, the S-SWIFT-R technique here proposed can be used as a part of a more complex hybrid technique, or as a component of a cross-layer protection strategy. In fact, our previous works [47,48] present some preliminary results of this, when tailored hybrid approaches are used by combining partial protection on both hardware and software (co-hardening). Unlike our previous approaches that were aimed at the hardware/software co-design, the presented proposal in this work focuses on the presentation of a new selective software-only fault recovery technique suitable for low-cost COTS -based applications.…”

Section: Related Workmentioning

confidence: 99%

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Selective SWIFT-R

et al. 2013

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Commercial off-the-shelf microprocessors are the core of low-cost embedded systems due to their programmability and cost-effectiveness. Recent advances in electronic technologies have allowed remarkable improvements in their performance. However, they have also made microprocessors more susceptible to transient faults induced by radiation. These non-destructive events (soft errors), may cause a microprocessor to produce a wrong computation result or lose control of a system with catastrophic consequences. Therefore, soft error mitigation has become a compulsory requirement for an increasing number of applications, which operate from the space to the ground level. In this context, this paper uses the concept of selective hardening, which is aimed to design reduced-overhead and flexible mitigation techniques. Following this concept, a novel flexible version of the software-based fault recovery technique known as SWIFT-R is proposed. Our approach makes possible to select different registers subsets from the microprocessor register file to be protected on software. Thus, design space is enriched with a wide spectrum of new partially protected versions, which offer more flexibility to designers. This permits to find the best tradeoffs between performance, code size, and fault coverage. Three case studies have been developed to show the applicability and flexibility of the proposal.

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Section: Discussionmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Selective SWIFT-R

et al. 2013

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“…A first software implementation of this technique was presented in [36] and tested on an Intel 8051 microcontroller. In [37], the authors present a new methodology that permits easy combination of hardware and software soft errors mitigation techniques and allows the automatic generation of protected source code, called hardened code.…”

Section: Harsh Condition Effects Mitigation On Programmable Cots Devicesmentioning

confidence: 99%

COTS – Harsh Condition Effects Considerations from Technology to User Level

Weide‐Zaage¹,

Payá-Vayá²

2017

Adv. sci. technol. eng. syst. j.

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“…The rest of them consist of typical small computations: bubble sort (BUB), Fibonacci (FIB), greatest common divisor (GCD), matrix addition (MADD), matrix multiplication (MM), scalar multiplication (MULT), exponentiation (POW), and quick sort (QSORT). In this case, fault injection tests were performed using the software-based simulation tool presented and validated in [22]. Table 1 presents the obtained results for the PicoBlaze case study.…”

Section: Case Study 1: Picoblazementioning

confidence: 99%

Application-Based Analysis of Register File Criticality for Reliability Assessment in Embedded Microprocessors

et al. 2015

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Abstract-There is an increasing concern to reduce the cost and overheads during the development of reliable systems. Selective protection of most critical parts of the systems represents a viable solution to obtain a high level of reliability at a fraction of the cost. In particular to design a selective fault mitigation strategy for processor-based systems, it is mandatory to identify and prioritize the most vulnerable registers in the register file as best candidates to be protected (hardened).This paper presents an application-based metric to estimate the criticality of each register from the microprocessor register file in microprocessor-based systems. The proposed metric relies on the combination of three different criteria based on common features of executed applications. The applicability and accuracy of our proposal have been evaluated in a set of applications running in different microprocessors. Results show a significant improvement in accuracy comparing to previous approaches and regardless the underlying architecture.

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Compiler-Directed Soft Error Mitigation for Embedded Systems

Cited by 47 publications

References 32 publications

Selective SWIFT-R

Selective SWIFT-R

COTS – Harsh Condition Effects Considerations from Technology to User Level

Application-Based Analysis of Register File Criticality for Reliability Assessment in Embedded Microprocessors

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