Compiler-directed physical address generation for reducing dTLB power

Kadayif, I.; Nath, Partho; Kandemir, Mahmut; Sivasubramaniam, Anand

doi:10.1109/ispass.2004.1291368

Cited by 14 publications

(15 citation statements)

References 6 publications

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“…A register holds the most recently used iTLB entry, and the compiler generates instructions that access only a register instead of the iTLB. That approach was extended later for the data TLB [33,34]. However, the TLBs are still used in such system.…”

Section: Related Workmentioning

confidence: 99%

“…TLBs have been reported to consume a significant fraction of processor energy [2,4,21,31,32,33]. The recent growth in the complexity of TLBs has further increased their energy consumption-a recent industrial report suggests that TLBs consume 3-13% of a processor's power [49].…”

Section: Introductionmentioning

confidence: 99%

“…Prior research focused on reducing the dynamic energy of TLBs through various techniques, such as optimizing TLB circuits [31], partitioning TLBs [10,17,18,37], filtering accesses to TLBs [11,17,21], dynamically resizing monolithic TLBs [9], virtual caches to access TLBs on L1 cache misses [14,29,52], and selectively avoiding TLB accesses [32,33,34]. However, these energy optimization techniques do not take into account hardware support for increasing the TLB reach (e.g., huge pages), that primarily targets improving performance and reducing static energy overheads due to TLB misses.…”

Section: Introductionmentioning

confidence: 99%

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Energy-efficient address translation

Karakostas

Gandhi

Cristal

et al. 2016

2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)

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Address translation is fundamental to processor performance. Prior work focused on reducing Translation Lookaside Buffer (TLB) misses to improve performance and energy, whereas we show that even TLB hits consume a significant amount of dynamic energy.To reduce the energy cost of address translation, we first propose Lite, a mechanism that monitors the performance and utility of L1 TLBs, and adaptively changes their sizes with way-disabling. The resulting TLB Lite organization opportunistically reduces the dynamic energy spent in address translation by 23% on average with minimal impact on TLB miss cycles. To further reduce the energy and performance overheads of L1 TLBs, we also propose RMM Lite that targets the recently proposed Redundant Memory Mappings (RMM) address-translation mechanism. RMM maps most of a process's address space with arbitrarily large ranges of contiguous pages in both virtual and physical address space using a modest number of entries in a range TLB. RMM Lite adds to RMM an L1-range TLB and the Lite mechanism. The high hit ratio of the L1-range TLB allows Lite to downsize the L1-page TLBs more aggressively. RMM Lite reduces the dynamic energy spent in address translation by 71% on average. Above the near-zero L2 TLB misses from RMM, RMM Lite further reduces the overhead from L1 TLB misses by 99%.These proposed designs target current and future energyefficient memory system design to meet the ever increasing memory demands of applications.

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Energy-efficient address translation

Karakostas

Gandhi

Cristal

et al. 2016

2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)

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“…Kadayif et al propose a compiler-directed physical address generation scheme to avoid DTLB accesses [10]. Several translation registers (TRs) are used to hold PPNs.…”

Section: Related Workmentioning

confidence: 99%

Improving data access efficiency by using a tagless access buffer (TAB)

Bardizbanyan

Gavin²,

Whalley³

et al. 2013

Proceedings of the 2013 IEEE/ACM International Symposium on Code Generation and Optimization (CGO)

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The need for energy efficiency continues to grow for many classes of processors, including those for which performance remains vital. Data cache is crucial for good performance, but it also represents a significant portion of the processor's energy expenditure. We describe the implementation and use of a tagless access buffer (TAB) that greatly improves data access energy efficiency while slightly improving performance. The compiler recognizes memory reference patterns within loops and allocates these references to a TAB. This combined hardware/software approach reduces energy usage by (1) replacing many level-one data cache (L1D) accesses with accesses to the smaller, more powerefficient TAB; (2) removing the need to perform tag checks or data translation lookaside buffer (DTLB) lookups for TAB accesses; and (3) reducing DTLB lookups when transferring data between the L1D and the TAB. Accesses to the TAB occur earlier in the pipeline, and data lines are prefetched from lower memory levels, which result in a small performance improvement. In addition, we can avoid many unnecessary block transfers between other memory hierarchy levels by characterizing how data in the TAB are used. With a combined size equal to that of a conventional 32-entry register file, a four-entry TAB eliminates 40% of L1D accesses and 42% of DTLB accesses, on average. This configuration reduces data-access related energy by 35% while simultaneously decreasing execution time by 3%.

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“…This in combination with two adaptive banked TLB designs proved to effectively improve the energy delay product of data TLBs. Kadayif et al [11] introduce translation registers (TR) to store the most frequently used TLB translations. During subsequent virtual address entries, these TRs are looked up and if present the information stored is used.…”

Section: Hardware Approachesmentioning

confidence: 99%

Code Transformations for TLB Power Reduction

Jeyapaul

Shrivastava

2010

Int J Parallel Prog

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The Translation Look-aside Buffer (TLB) is a very important part in the hardware support for virtual memory management implementation of high performance embedded systems. The TLB though small is frequently accessed, and therefore not only consumes significant energy, but also is one of the important thermal hot-spots in the processor. Recently, several circuit and microarchitectural implementations of TLBs have been proposed to reduce TLB power. One simple, yet effective TLB design for power reduction is the Use-Last TLB architecture proposed in IEEE J Solid State Circuits, 1190-1199, (2004). The Use-Last TLB architecture reduces the power consumption when the last page is accessed again. In this work, we develop code transformation techniques to reduce the page switchings in data cache accesses and propose an efficient page-aware code placement technique to enhance the energy reduction capabilities achieved by the Use-Last TLB architecture for instruction cache accesses. Our comprehensive page switch reduction algorithm results in an average of 39% reduction in the data-TLB page switching, and our code placement heuristic results in an average of 76% reduction in the instrucion-TLB page switchings with negligible impact on the performance on benchmarks from MiBench, Multimedia, DSPStone and BDTI suites. The reduced page switch count through our techniques achieves an equivalent power savings, above and beyond the reduction achieved by the Use-Last TLB architecture implementation.

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Compiler-directed physical address generation for reducing dTLB power

Cited by 14 publications

References 6 publications

Energy-efficient address translation

Energy-efficient address translation

Improving data access efficiency by using a tagless access buffer (TAB)

Code Transformations for TLB Power Reduction

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