Compile-time program restructuring in multiprogrammed virtual memory systems

Hartley, Stephen J.

doi:10.1109/32.9051

Cited by 30 publications

(6 citation statements)

References 21 publications

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“…Code layout optimizations were originally proposed to reduce the working set size of applications for virtual memory [8,10,11]. More recent work has focused on the reduction of branch mispredicts and cache misses.…”

Section: Discussion and Related Workmentioning

confidence: 99%

Code layout optimizations for transaction processing workloads

Ramírez

Barroso²,

Gharachorloo³

et al. 2001

Proceedings of the 28th Annual International Symposium on Computer Architecture - ISCA '01

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Commercial applications such as databases and Web servers constitute the most important market segment for high-performance servers. Among these applications, on-line transaction processing (OLTP) workloads provide a challenging set of requirements for system designs since they often exhibit inefficient executions dominated by a large memory stall component. This behavior arises from large instruction and data footprints and high communication miss rates. A number of recent studies have characterized the behavior of commercial workloads and proposed architectural features to improve their performance. However, there has been little research on the impact of software and compiler-level optimizations for improving the behavior of such workloads.This paper provides a detailed study of profile-driven compiler optimizations to improve the code layout in commercial workloads with large instruction footprints. Our compiler algorithms are implemented in the context of Spike, an executable optimizer for the Alpha architecture. Our experiments use the Oracle commercial database engine running an OLTP workload, with results generated using both full system simulations and actual runs on Alpha multiprocessors. Our results show that code layout optimizations can provide a major improvement in the instruction cache behavior, providing a 55% to 65% reduction in the application misses for 64-128K caches. Our analysis shows that this improvement primarily arises from longer sequences of consecutively executed instructions and more reuse of cache lines before they are replaced. We also show that the majority of application instruction misses are caused by self-interference. However, code layout optimizations significantly reduce the amount of self-interference, thus elevating the relative importance of interference with operating system code. Finally, we show that better code layout can also provide substantial improvements in the behavior of other memory system components such as the instruction TLB and the unified second-level cache. The overall performance impact of our code layout optimizations is an improvement of 1.33 times in the execution time of our workload.

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Section: Discussion and Related Workmentioning

confidence: 99%

Code layout optimizations for transaction processing workloads

Ramírez

Barroso²,

Gharachorloo³

et al. 2001

Proceedings of the 28th Annual International Symposium on Computer Architecture - ISCA '01

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“…For example, Hatfield and Gerald [16] reorder code sectors to have parts close to each other if they are used together. Similarly, Hartley [15] duplicates code blocks to have functions always near their caller. However, these optimizations do not modify the arrangement of variables in memory.…”

Section: Related Workmentioning

confidence: 98%

Removing the memory limitations of sensor networks with flash-based virtual memory

Lachenmann

Marrón

Gauger

et al. 2007

Proceedings of the 2nd ACM SIGOPS/EuroSys European Conference on Computer Systems 2007

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Virtual memory has been successfully used in different domains to extend the amount of memory available to applications. We have adapted this mechanism to sensor networks, where, traditionally, RAM is a severely constrained resource. In this paper we show that the overhead of virtual memory can be significantly reduced with compile-time optimizations to make it usable in practice, even with the resource limitations present in sensor networks.Our approach, ViMem, creates an efficient memory layout based on variable access traces obtained from simulation tools. This layout is optimized to the memory access patterns of the application and to the specific properties of the sensor network hardware.Our implementation is based on TinyOS. It includes a pre-compiler for nesC code that translates virtual memory accesses into calls of ViMem's runtime component. ViMem uses flash memory as secondary storage. In order to evaluate our system we have modified nontrivial existing applications to make use of virtual memory. We show that its runtime overhead is small even for large data sizes.

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“…Kernel is used to write the contents of currently unused block of memory to the hard disk .so the memory can be used for some purpose presented in Hartley S.J. [7].…”

Section: IIImentioning

confidence: 99%

An Efficient Virtual Memory using Graceful Code

YA¹

2019

IJTSRD

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Memory is hardware that is used by computer to load the operating system and run programs. It is buildup of RAM chip that has different memory modules. The amount of main memory in a computer is limited to the amount of RAM that has installed. Generally memory sizes are 256 MB, 512 MB, & 1 GB, because of computer has limited amount of RAM. When too many programs are simultaneously it is possible to run a program out of memory. This is the concept where virtual memory comes. Virtual memory enhance the available memory of a computer has by enlarging the address space or place in memory where data can be stored. Hard disk is used for additional memory allocation .However, since secondary storage is much slower than the RAM, program which is in Virtual Memory must be mapped back to virtual memory in order to be used. The process of mapping data and forth between the hard disc and RAM takes longer than accessing it directly from the memory. It means virtual memory is increased, the more it will slow your computer down. While virtual memory enables your computer to run more than one program it could, otherwise it is the best way to having as main memory as possible.

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Compile-time program restructuring in multiprogrammed virtual memory systems

Cited by 30 publications

References 21 publications

Code layout optimizations for transaction processing workloads

Code layout optimizations for transaction processing workloads

Removing the memory limitations of sensor networks with flash-based virtual memory

An Efficient Virtual Memory using Graceful Code

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