Compilation tools for run-time reconfigurable designs

Luk, Wayne; Shirazi, N.; Cheung, Peter Y. K.

doi:10.1109/fpga.1997.624605

Cited by 63 publications

(40 citation statements)

References 11 publications

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“…Previously we reported a model [11] and the associated development tools [12] for reconfigurable designs. In this model, a component that can be configured to behave either as A or as B is described by a network with A and B connected between two control blocks.…”

Section: Multiplexer-based Reconfigurationmentioning

confidence: 99%

Reconfigurable design with clock gating

Osborne¹,

Luk²,

Coutinho³

et al. 2008

2008 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation

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This paper describes an approach for developing energyoptimized run-time reconfigurable designs which benefit from clock gating. The approach is applied to two techniques: multiplexer-based reconfiguration, and reconfigurable wordlength optimization. The conditions under which this approach would be preferable to bit-stream reconfiguration are derived. Various case studies, such as ray tracing, guitar string simulation and matrix-vector multiplication, are used to illustrate this approach.

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Section: Multiplexer-based Reconfigurationmentioning

confidence: 99%

Reconfigurable design with clock gating

Osborne¹,

Luk²,

Coutinho³

et al. 2008

2008 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation

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“…If the reconfiguration sequence is known at compile time, then control blocks which model the run-time selection of components in a particular sequence can be used [6]. At present Pebble descriptions are translated into the EDIF format, for which a set of tools has been developed to produce reconfigurable designs [8]. We are exploring language support for reconfiguration by having, for instance, a RECONFIGURE-IF statement (Fig.…”

Section: Support For Reconfigurationmentioning

confidence: 99%

“…Pebble supports the development of run-time reconfigurable circuits based on the model for reconfigurable designs in [8]. In this model, a component that can be configured to behave either as A or as B is described by a network with A and B connected between two control blocks.…”

Section: Support For Reconfigurationmentioning

confidence: 99%

Pebble: A language for parametrised and reconfigurable hardware design

Luk

McKeever

1998

Lecture Notes in Computer Science

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Abstract. Pebble is a simple language designed to improve the productivity and effectiveness of hardware design. It improves productivity by adopting reusable word-level and bit-level descriptions which can be customised by different parameter values, such as design size and the number of pipeline stages. Such descriptions can be compiled without flattening into various VHDL dialects. Pebble improves design effectiveness by supporting optional constraint descriptions, such as placement attributes, at various levels of abstraction; it also supports run-time reconfigurable design. We introduce Pebble and the associated tools, and illustrate their application to VHDL library development and reconfigurable designs for Field Programmable Gate Arrays (FPGAs).

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“…al reported in [12] and to a lesser extent in [13]. The dynamic selection scheme we present here is a little more general than Luk's RC_MUX mechanism, which requires all the alternatives to have inputs of the same type and an output of the same type (at the bit level) as shown in Figure 3.…”

Section: Dynamic Selectionmentioning

confidence: 93%

Interface specification for reconfigurable components

Singh¹

IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002.

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This paper presents a way of encoding some kinds of dynamic reconfiguration behaviour in the interface portion of circuit descriptions. This has many advantages. The user of a reconfigurable circuit has some knowledge about the reconfigurable interface of the circuit. Static analysis tools can make better decisions about how to schedule virtual hardware. And most importantly the compiler can automatically synthesize the required interface between reconfigurable portions of the system and the regular portions of the design. Several existing models of dynamic reconfiguration from the literature are captured using our type system extension based on sum types. This is especially important in System-on-Chip (SoC) contexts where a reconfigurable IP block may have to communicate over a non-trivial IP bus like CoreConnect TM .

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Compilation tools for run-time reconfigurable designs

Cited by 63 publications

References 11 publications

Reconfigurable design with clock gating

Reconfigurable design with clock gating

Pebble: A language for parametrised and reconfigurable hardware design

Interface specification for reconfigurable components

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