Compilation of Parallel Data Access for Vector Processor in Radio Base Stations

Chen, Wei; Peng, Hao; Liu, Dake; Bai, Yong

doi:10.1109/les.2021.3085664

Cited by 2 publications

(1 citation statement)

References 14 publications

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“…The team in our laboratory has developed a set of very long instruction word (VLIW) vector processing for baseband processing MCU + load/store + single instruction multiple data (SIMD). The specific architecture is described in [25]. The processor platform is based on an SIMD kernel design with variable data-level parallelism.…”

Section: Vector Processor Instruction Set Architecturementioning

confidence: 99%

An Uplink Channel Estimator Using a Dedicated Instruction Set for 5G Small Cells

Long

Liu

Sun

2022

Sensors

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As 5G small cells gradually become the main force of 5G indoor deployment, it is necessary to study channel estimators for 5G small base stations, but there has been limited research on high-performance channel estimators in recent years. This study implemented a low-delay, low-overhead, relatively universal channel estimation module by dedicated instruction set acceleration including reference signal estimation, Wiener, 1st order, and 2nd order interpolations in frequency and time domains. The instruction level acceleration is on our vector processor, yet is suitable for other commercial and academic vector processors. Through instruction acceleration, compared with the existing general vector processing instruction sets, the processor performance of the LS estimation module and Wiener filter interpolation in the frequency domain is improved by 50% and 37.5%, respectively. The BER VS SNR measure of time–frequency Wiener filter interpolation achieves 4 db compared with linear interpolation, meaning our instruction level acceleration can be an optimum solution.

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Section: Vector Processor Instruction Set Architecturementioning

confidence: 99%