Comparitive analysis of null convention logic and synchronous CMOS ripple carry adders

Vakil, Akash; Jayadev, K. P.; Hegde, Sandesh; Koppad, Deepali

doi:10.1109/icecct.2017.8117926

Cited by 5 publications

(3 citation statements)

References 4 publications

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“…In this section, we use the full adder model [26] as an example for testing the library that we generated based on our proposed flow. This model comprises two th23 gates and two th34w2 gates, as shown in Figure 21, and its output equations are as follows:…”

Section: The Synthesis Results Of the Rtl Codementioning

confidence: 99%

A Methodology to Design Static NCL Libraries

Le-Thanh

Tri

Hoang

2022

JLPEA

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The Null Convention Logic (NCL) based asynchronous design technique has interested researchers because this technique had overcome disadvantages of the synchronous technique, such as noise, glitches, clock skew and power. However, using the NCL-based asynchronous design method is difficult for university students and researchers because of the lack of standard NCL cell libraries. Therefore, in this paper, a novel flow is proposed to design NCL cell libraries. These libraries are used to synthesize NCL-based asynchronous designs. We chose the static NCL cell library to illustrate the proposed design solution because this library is one of the most basic NCL libraries. Static NCL cells in this library are designed based on the Process Design Kit 45nm technology and are implemented by the Virtuoso and the Design Compiler (DC) tool. In addition, the Ocean script and Electronic Design Automation (EDA) environment are used for supporting designs and simulations. A complete library of 27 NCL cells was designed to serve for study and research. We also implemented synthesis for NCL full adders using this library and compared our synthesis results with the results of other authors. The comparison results indicated that our results were a 20% improvement on power consumption.

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Section: The Synthesis Results Of the Rtl Codementioning

confidence: 99%

A Methodology to Design Static NCL Libraries

Le-Thanh

Tri

Hoang

2022

JLPEA

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“…On the other hand, in [19], 1 bit, 4 bit and 8 bit NCL ripple carry adders have been designed and compared with the corresponding ripple carry adders implemented using conventional synchronous complementary metaloxide-semiconductor (CMOS) level design methodologies. The synthesis results in [19] indicated that NCL circuits have a significant decrease (about 65%) in power consumption. Both above mentioned models in [18,19] were carried out on a small scale designs.…”

Section: Introductionmentioning

confidence: 99%

“…The synthesis results in [19] indicated that NCL circuits have a significant decrease (about 65%) in power consumption. Both above mentioned models in [18,19] were carried out on a small scale designs. Thus, in this paper, we would like to use a large scale design to demonstate more clearly the low power advantage of the NCL based asynchronous design technique.…”

Section: Introductionmentioning

confidence: 99%

Low power circuit design using NCL based asynchronous method

Le-Thanh

Tri

Hoang

2021

IJEECS

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The null convention logic (NCL) based circuit design methodology eliminates the problems related to noise, clock tree, electromagnetic interference and also reduces significant power consumption. In this paper, we would like to demonstrate the advantage of low power consumption of the NCL based asynchronous circuit design on a large design scale, thus we used the advanced encryption standard (AES) encryption design as an illustrative example. In addition, we also proposed two pipelined AES encryption models using the synchronous circuit design technique and the asynchronous circuit design technique based on NCL. Besides, these two models were realized by using version control system (VCS) tool to simulate and Design Compiler tool to synthesize parameters in power consumption, processing speed and area. The synthesis results of these two models indicated that power consumption of the NCL based asynchronous AES encryption model had a decrease of 71% compared with the synchronous AES encryption model. Moreover, we show the outstanding advantage of the power consumption of the NCL based asynchronous design model (a decrease of 91.12% and 93,23%) compared to the synchronous design model using clock gating technique and without using clock gating technique respectively.

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