Comparison of TiSi2 , CoSi2, and NiSi for Thin‐Film Silicon‐on‐Insulator Applications

Abstract

TiSi2, CoSi2, and NiSi self-aligned silicide processes have been studied, compared, and applied to thin-film siliconon-insulator technology. Compared to TiSi5, CoSi2 and NiSi have the advantages of wider process temperature window, no significant doping retarded reaction, narrow runner degradation, and thin-film degradation. Therefore, they are more suitable for thin-film silicon-on-insulator technology. N-type field effect transistors have been fabricated in a complementary metal oxide-semiconductor compatible thin-film silicon-on-insulator technology with titanium, cobalt, and nickel self-aligned silicide processes for low-voltage, low-power microwave applications. The initial thicknesses of titanium, cobalt, and nickel are 30, 13, and 25 nm, respectively. The gate sheet resistances are 6.2, 4.4, and 2.9 fl/Q, respectively, and the total source/drain series resistances are 700, 290, and 550 Cl m, respectively. High-frequency measurement results are also presented. InfroductionThin-film silicon-on-insulator, metal oxide-semiconductor field-effect transistors (TFSOI MOSFETS) are now considered good candidates for high-speed, low-voltage, low-power applications because of their quasi-ideal properties, such as high current drivability, low body effect, and low parasitic capacitances.1 It has been reported that SOl MOSFETs fabricated on high-resistivity substrates separated by implanted oxgyen (SIMOX) wafers, with a nonstandard complementary metal oxide-semiconductor (CMOS) process using metal gate and air-bridge metallization, offer interesting microwave performance.2Recently, it has been demonstrated that a 0.75 sm fully depleted TFSOI n-MOSFET fabricated with a CMOScompatible process, with a 30 nm thick TiSi5 layer on both gate and source/drain areas, presents a maximum oscillation frequency of 11 GHz for a supply voltage of 0.9 V. This kind of device is suitable for low-voltage, low-power telecommunication applications.The TiSi7 self-aligned silicide (SALICIDE) process is widely used in bulk CMOS technology to reduce series resistance and gate sheet resistance.4'5 It has been reported that the TiSi5 process encounters a lot of problems in scaled devices. Indeed, the titanium silicidation reaction is not only sensitive to the doping concentration in silicon substrate, but it is also sensitive to silicide film thickness.6'7 Until now, it is still difficult to apply a TiSi5 SALI-CIDE process to TFSOI technology, mainly because of the limited thickness of the active silicon layer.6'9 A very narrow process temperature window is observed in our experiments to use a TiSi5 process on TFSOI MOSFETs.1°F urthermore, the series resistance of an SOl MOSFET with a SALICIDE process is also sensitive to silicide thickness, the optimized condition is to keep the silicide layer thickness less than 80% of the original active silicon layer thickness.1' Therefore, for a TFSOI MOSFET with an 80 nm thick active silicon layer, the thickness of silicide should be thinner than 64 nm to secure a low contact resistance.Recently, it has bee...

Spontaneous Growth of Highly Conductive Two‐Dimensional Single‐Crystalline TiSi2 Nanonets

“…TiSi 2 is an excellent electronic material as it is one of the most conductive silicides (resistivity % 10 mW cm). [6,7] TiSi 2 was also recently shown to be a good photocatalyst for splitting H 2 O by absorbing visible light, which is a promising approach toward solar-generated H 2 as a clean energy carrier.[8] The improved charge-transport properties offered by complex nanoscale structures of TiSi 2 are desirable for nanoelectronics and solar energy harvesting. Their chemical synthesis is thus appealing; however, the synthetic conditions required by the two key features of complex nanostructures, low dimensionality and complexity, seem to contradict each other.…”

Silicon‐on‐insulator MOSFETs models in analog/RF domain

“…Today, new channel materials are considered such as Ge and III–V for holes and electrons transport, respectively. Raised source and drain regions and silicidation as well as low Schottky barrier source and drain contacts have been proposed those last years to minimize their impact on the static and dynamic transistor behaviors. Modification of the device architecture such as introduction of faceted source and drain , low‐k spacer materials , gate capping layer thickness, and gate height have been used recently to reduce the fringing parasitic capacitance effect.…”

Influence of temperature, metal layer, and groove angle in the nanowire growth: a prospective study on nickel silicide nanowires

“…NiSi NWs have many advantages over the other silicide NWs such as TiSi 2 and CoSi 2 . They are less consumption of Si which is important for shallow junctions, formation of NWs at comparatively low temperature, and low Shottky barrier height (Iwai et al 2002;Chen et al 1997). Moreover, NiSi NWs exhibit low stress and resistant to most of the Si etchants like potassium hydroxide (Qin et al 2000;Bhaskaran et al 2007).…”