Comparison of three different architectures for MOS-compatible quadratic synapses

Abstract

Inspired by the harmony between the basic functional elements of biological neural networks and their natural operating media, we have been seeking for ways to implement Artificial Neural Networks ( A N N s ) using the intrinsic functionality of the most commonly available devices in an electronics technology, in contrast to the method of hardware-compilation of softwaresimulation modules. In the case of MOS technology, we employ a quadratic functional equation similar to that found in standard MOS transistors to implement synapses in ANNs. A structure has been proposed in [3] to implement a MOS device with extemally-controllable threshold voltage to be employed as a synapse. In the present work, we develop and compare practical architectures within which these synapses can be utilized optimally. A simulator and proper training algorithms have been developed to simulate different hardware-based architectures.