Comparison of thin film cracking and delamination for aluminum and copper silicon interconnects with organic packaging

He, Dedong; Zhang, C.; Chiang, D.; Zheng, Tieyu; Lucero, Alan; Stage, Roger; Atluri, V.

doi:10.1109/ectc.2005.1441290

Cited by 3 publications

(1 citation statement)

References 5 publications

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“…[4] This crack affects the induced stresses in the weak and defect riddled low-K ILD layer and it has been theorized that when the passivation layer crack reaches a critical length, RLD catastrophic failure is expected to occur as depicted in Figure 4.…”

Section: Two-dimensional Fracture Mechanics Based Modelingmentioning

confidence: 99%

A Review of First Level Interconnect Modeling Methodology

Dimagiba¹,

Ganapathysubramanian

Modi

2006

2006 Thirty-First IEEE/CPMT International Electronics Manufacturing Technology Symposium

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The paradigm shifts within the microelectronics industry, such as the introduction of highly fragile low-k dielectric films and the shift to leadfree solders, have introduced a host of highly localized thermo-mechanical packaging stress issues. One of these issues is the impact of packaging stresses on low-K inter-layer dielectric (ILD) materials in the die backend. With increasing design complexity, conventional numerical analysis methodologies are proving ineffective in providing a reasonable risk assessment and design improvement strategy. New design tools and methodologies are being aggressively developed for the accurate representation of localized regions of the interconnect and the substrate to determine the level of package-induced stress on the die backend. This paper reviews modeling methodologies particularly relating to ILD delamination and the continuing progression in developing further understanding of the failure mechanisms.

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Section: Two-dimensional Fracture Mechanics Based Modelingmentioning

confidence: 99%