Comparison of the Threshold-Voltage Stability of SiC MOSFETs with Thermally Grown and Deposited Gate Oxides

Abstract

The electrical characteristics and the reliability of different oxides on the 4H-SiC Si-face for gate oxide application in MOS devices are compared under MOSFET operation conditions at room temperature, at 100°C and at 130°C. The oxides are either an 80nm thick deposited oxide annealed in NO or an 80nm thick grown oxide in diluted N2O. The deposited oxide shows significant higher QBD- and lower Dit-values as well as a stronger decrease of drain current under stress than the grown oxide. Although for the deposited oxide, the leakage current below subthreshold increases more than one order of magnitude during constant circuit stress at room temperature, for the thermal oxide it is quite constant, but at higher level for higher temperatures.

(Invited) Effect of Threshold-Voltage Instability on SiC Power MOSFET High-Temperature Reliability

“…With the continued advances reported in SiC power MOSFET performance, more and more attention is being turned to device reliability [5][6][7]. Among reliability concerns, an important remaining issue is the instability in the threshold voltage under bias and temperature stress [5,[7][8][9][10][11]. This paper reviews recent results from our group, with special attention paid to effects at elevated temperatures where these power devices would be expected to operate.…”

Reliability study on positive bias temperature instability in SiC MOSFETs by fast drain current measurement

“…However, SiC devices have unresolved reliability issues 2) such as gate threshold voltage (V th ) instability in SiC MOSFETs caused by gate bias stress. [3][4][5][6][7][8][9][10][11][12] This is because the SiC MOS has various carrier trap sites owing to a high density of interface states and defects in the gate oxide SiO 2 . The V th instability is caused by injected and captured charges in the trap sites of gate oxide or the MOS interface and=or the generation of new defect sites such as interface states due to gate bias stress.…”

“…[13][14][15][16] Many studies have focused on how to improve this V th instability issue. [6][7][8][9][10][11][12] Since positive bias temperature stress (PBTS) is applied to the gate of MOSFETs to operate an n-channel power MOSFET, it is considered that positive bias temperature instability (PBTI) is a more important issue than negative bias temperature instability (NBTI).…”

Threshold-voltage bias-temperature instability in commercially-available SiC MOSFETs

“…As such, it has been studied by a number of different research groups in recent years. [2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19] This work reports on three important aspects of the issue: (1) the V T instability observed in commercial devices, (2) a summary of the basic mechanisms driving this instability, and (3) the need for an improved test method for evaluating these devices; but the emphasis is on the V T bias-temperature instability observed in commercially-available SiC MOSFETs.…”