Comparison of QMC-based yield-aware pareto front techniques for multi-objective robust analog synthesis

Pak, Murat; Fernandez, F.V.; Dündar, Günhan

doi:10.1016/j.vlsi.2016.04.004

Cited by 11 publications

(4 citation statements)

References 18 publications

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“…In [22], clustering is used to select a subset of the representative solutions to be subject to MC analysis at each iteration. Some other works adopted low-discrepancy sequences methods to reduce the necessary number of MC samples; however, their use in optimization-based methodologies still demands many simulations [23], [24]. In [25], [26], system-level designs considering the yield estimation are reached.…”

Section: A Rf Ic Variability-aware Synthesismentioning

confidence: 99%

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Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICs

et al. 2021

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This paper presents an innovative yield-aware synthesis strategy based on a hierarchical bottom-up methodology that uses a multiobjective evolutionary optimization algorithm to design a complete radiofrequency integrated circuit from the passive component level up to the system level. Within it, performances' calculation aims for the highest possible accuracy. A surrogate model calculates the performances for the inductive devices, with accuracy comparable to full electromagnetic simulation; and, an electrical simulator calculates circuit-and system-level performances. Yield is calculated using Monte-Carlo (MC) analysis with the foundry-provided models without any model approximation. The computation of the circuit yield throughout the hierarchy is estimated employing parallelism and reducing the number of simulations by performing MC analysis only to a reduced number of candidate solutions, alleviating the computational requirements during the optimization. The yield of the elements not accurately evaluated is assigned using their degree of similitude to the simulated solutions. The result is a novel synthesis methodology that reduces the total optimization time compared to a complete MC yield-aware optimization. Ultimately, the methodology proposed in this work is compared against other methodologies that do not consider yield throughout the system's complete hierarchy, demonstrating that it is necessary to consider it over the entire hierarchy to achieve robust optimal designs.

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Section: A Rf Ic Variability-aware Synthesismentioning

confidence: 99%

“…3 shows the typical behaviour of the standard deviation of an objective versus the yield value. Nevetheles, if needed, the yield can be computed considering the variability of the optimization objectives explicitly, as done in [24] instead.…”

Section: Yield Estimation Across the Hierarchymentioning

confidence: 99%

Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICs

et al. 2021

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“…The points in the sequence are generated to satisfy a uniform coverage among the sampling space. MC simulations which are using these deterministic sequences instead of the pseudorandom sequences are called Quasi-Monte Carlo (QMC) [17]. In this work, a QMC-based methodology has been implemented to accurately estimate the yield of the mixed-domain MEMS.…”

Section: Yield Estimation Techniques and Selection Of Qmc-based Metho...mentioning

confidence: 99%

Yield-aware multi-objective optimization of a MEMS accelerometer system using QMC-based methodologies

Pak

Fernández

Dündar

2020

Microelectronics Journal

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“…The alternative approach proposed here consists of a cooptimization process of the whole MEMS, where the sensor performance is evaluated first at each iteration of the optimization loop, and, then, these results are used for circuit level simulations, both performed within the same optimization loop. The optimal performances are obtained by using a powerful evolutionary algorithm, namely MOEA/D [14][15], that has been implemented in Matlab. The proposed technique is expected to bring solutions to the specification partitioning problem since such partitioning disappears from the design process.…”

Section: System Level Design Variablesmentioning

confidence: 99%

A novel design methodology for the mixed-domain optimization of a MEMS accelerometer

Pak

Fernandez²,

Dündar

2018

Integration

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This paper proposes a novel optimization-based design methodology that can be used for mixed-domain synthesis of MEMS accelerometers. Several problems have been identified with existing methodologies and comparative experiments that demonstrate the superiority of the proposed methodology are performed. Highly accurate analytical models of the MEMS accelerometer device have been used for the evaluation of the MEMS sensor performances in the mixed-domain optimization. The circuit level simulations, on the other hand, are based on an electrical simulator, e.g., Hspice. The implemented methodology has been tested on the optimization of a MEMS accelerometer that includes a capacitive MEMS sensor and an analog read-out circuitry.

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Comparison of QMC-based yield-aware pareto front techniques for multi-objective robust analog synthesis

Cited by 11 publications

References 18 publications

Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICs

Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICs

Yield-aware multi-objective optimization of a MEMS accelerometer system using QMC-based methodologies

A novel design methodology for the mixed-domain optimization of a MEMS accelerometer

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