2013 Asilomar Conference on Signals, Systems and Computers 2013
DOI: 10.1109/acssc.2013.6810473
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Comparison of parallelized radix-2 and radix-4 scalable Montgomery multipliers

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“…In each kernel cycle of Montgomery modular multiplication with [19], it shifts operands M$M$ and A$A$ 1 bit left n/w$n/w$ times with temporary results Z:=Z+qi·M+bi·A$Z:= Z+ q_i\cdot M+ b_i\cdot A$, and then right shift the result n/w$n/w$ bits 1 time at the end of the kernel cycle with Z:=Z/2n/w$Z:= Z/2^{n/w}$ [20], that is, performing the division of 2n/w$2^{n/w}$ in (Z+qi·M+bi·A)/2n/w$(Z+ q_i\cdot M+ b_i\cdot A)/2^{n/w}$ from serial operation to one‐step operation. In this way, the latency between processing elements is decreased from 2 clock cycles to 1 clock cycle.…”
Section: Hardware Implementationmentioning
confidence: 99%
“…In each kernel cycle of Montgomery modular multiplication with [19], it shifts operands M$M$ and A$A$ 1 bit left n/w$n/w$ times with temporary results Z:=Z+qi·M+bi·A$Z:= Z+ q_i\cdot M+ b_i\cdot A$, and then right shift the result n/w$n/w$ bits 1 time at the end of the kernel cycle with Z:=Z/2n/w$Z:= Z/2^{n/w}$ [20], that is, performing the division of 2n/w$2^{n/w}$ in (Z+qi·M+bi·A)/2n/w$(Z+ q_i\cdot M+ b_i\cdot A)/2^{n/w}$ from serial operation to one‐step operation. In this way, the latency between processing elements is decreased from 2 clock cycles to 1 clock cycle.…”
Section: Hardware Implementationmentioning
confidence: 99%