Comparison of Parallel and Deductive Fault Simulation Methods

Chang, H. Y.; Chappell, S.G.; Elmendorf, C. H.; Schmidt, L.

doi:10.1109/t-c.1974.223820

Cited by 37 publications

(7 citation statements)

References 6 publications

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“…This paper is concerned with developing an efficient method for S-A fault simulation, i.e., to determine exactly all S-A faults which are covered by a given test pattern. All previously known methods [3,4,6,[20][21][22][23][24][25][26][27][28][29][30] for S-A fault simulation of a general Boolean circuit of size n require cn ~ time for some constant c _> 1. This quadratic time bound is already very costly for moderate size LSI since if n >__ 104, then at least n 2 -1010 steps required by these previous methods seems unfeasible even on the fastest known sequential machine.…”

Section: I$ Previous Work In Fault Simulationmentioning

confidence: 99%

Efficient VLSI fault simulation

Reif

1993

Computers & Mathematics with Applications

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Section: I$ Previous Work In Fault Simulationmentioning

confidence: 99%

Efficient VLSI fault simulation

Reif

1993

Computers & Mathematics with Applications

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“…This is generally a subset of the faults listed in the fault dictionary, and only this subset for which a test pattern propagates, is simulated against this pattern. This reduction in faults results in significant savings of computer resource [9]· The major disadvantage of deductive fault simulation is the unpredictable amount of storage required for the long fault lists. This disadvantage is less significant today, since com puters have virtual storage.…”

Section: Fault Simulation and Verificationmentioning

confidence: 99%

“…In general, however, only the continuing simulation against all faults, and retaining them after first detection, provides full diagnostic capability. This mode of continuing fault simulation against all faults is sometimes also referred to as "full dictio nary mode" [9].…”

Section: Fault Simulation and Verificationmentioning

confidence: 99%

LSI logic testing — An overview

Muehldorf

Savkar

1981

IEEE Trans. Comput.

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In this paper the development of large scale integration (LSI) testing is reviewed. The paper concentrates on the testing of logic components and presents in-depth discussions of the methods of fault modeling, test pattern generation, fault simulation, and design for testability. It is shown how these methods are used in the design of components and how they can be used in support of design automa tion.Finally, a brief account of test equipment and test data preparation is given.

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“…In design and test, three main forms of describing processes and phenomena are used: tabular, analytical, graph [1][2][3][4][5][6]. In this case, the matrix (table) and the vector are two forms for describing models that pass into each other.…”

mentioning

confidence: 99%

“…• High computational complexity of combinatorial analysis algorithms at the register level of model description [2,[4][5][6][7][14][15][16][17][18][19][20][21][22].…”

mentioning

confidence: 99%

Vector-deductive Memory-based Transactions for Fault-as-address Simulation

Gharibi¹,

Hahanova²,

Hahanov³

et al. 2023

Èlektron. model.

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The main idea is to create logic-free vector computing, using only read-write transactions on address memory. The strategic goal is to create a deterministic vector-quantum computing using photons for read-write transactions on stable subatomic memory elements. The main task is to implement new vector computing models and methods based on primitive read-write transactions in vector flexible interpretive fault modeling and simulation technology, where data is used as addresses for processing the data itself. The essence of vector computing is read-write transactions on vector data structures in address memory. Vector computing is a computational process based on elementary read-write transactions over cells of binary vectors that are stored in address memory and form a functionality where the input data to be processed is the addresses of these cells. The advantages of a vector universal model for a compact description of ordered processes, phenomena, functions, and structures are defined for the purpose of their parallel analysis. Analytical expressions of logic, which require algorithmically complex calculators, are replaced by output state vectors of elements and digital circuits, focused on the parallelism of register logical procedures on regular data structures. A vector-deductive method for formula synthesis for propagating input lists (data) of faults is proposed, which has a quadratic computational complexity of register operations. A new matrix of deductive vectors has been synthesized, which is characterized by the following properties: compactness, parallel data processing based on a single read-write transaction in memory, elimination of traditional logic from fault simulation procedures, full automation of its synthesis process, and focus on technological solving all problems of technical diagnosis. In the work, the transition to vector logic in the organization of computing and the elimination of traditional logic presented in the form of tables and analytical expressions were carried out. The use of read-write transactions on memory in the absence of a command system focuses the new vector-logic computing towards deterministic quantum architectures based on stable subatomic memory particles.

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Comparison of Parallel and Deductive Fault Simulation Methods

Cited by 37 publications

References 6 publications

Efficient VLSI fault simulation

Efficient VLSI fault simulation

LSI logic testing — An overview

Vector-deductive Memory-based Transactions for Fault-as-address Simulation

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