Comparison of floating gate neural network memory cells in standard VLSI CMOS technology

Durfee, D.A.; Shoucair, F.S.

doi:10.1109/72.129407

Cited by 25 publications

(7 citation statements)

References 21 publications

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“…53,54 These strive to reduce the tunnelling voltage, while increasing the tunnelling current (and thus reducing the programming time required). Textured polysilicon may make floatinggate programming requirements less demanding, while floating-gate structures may be feasible within a standard CMOS process.…”

Section: Floating-gate (Eeprom) Technologymentioning

confidence: 99%

The Prospects for Analogue Neural VLSI

Murray

Woodburn

1997

Int. J. Neur. Syst.

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In recent years, the efforts of analogue, neural-hardware designers have shifted from generic analogue neurocomputers to "niche" markets in sensor fusion and robotics, and we explain why this is so. We describe the main differences between digital and analogue computation, and consider the advantages of pure analogue and pulsed methods of design. We then investigate some important issues in analogue design of neural machines, namely weight storage (volatile and non-volatile), on-chip learning, and arithmetic accuracy and its relationship to noise. Finally, we outline those areas in which analogue techniques are likely to prove most useful, and speculate as to their likely long-term utility.

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Section: Floating-gate (Eeprom) Technologymentioning

confidence: 99%

The Prospects for Analogue Neural VLSI

Murray

Woodburn

1997

Int. J. Neur. Syst.

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“…Floating-gate synapses offer an alternative to capacitive analog memory [3,4]. Floating-gate storage also boasts small layout areas, but requires special highvoltage programming circuitry on chip.…”

Section: Introductionmentioning

confidence: 99%

An MDAC synapse for analog neural networks

Kier

Harrison

Beer

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)

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Efficient weight storage and multiplication are important design challenges which must be addressed in analog neural network implementations. Many schemes which treat storage and multiplication separately have been previously reported for implementation of synapses. We present a novel synapse circuit that integrates the weight storage and multiplication into a single, compact multiplying digital-to-analog converter (MDAC) circuit. The circuit has a small layout area (5400 µm 2 in a 1.5-µm process) and exhibits good linearity over its entire input range.We have fabricated several synapses and characterized their responses. Average maximum INL and DNL values of 0.2 LSB and 0.4 LSB, respectively, have been measured. We also report on the performance of an analog recurrent neural network which uses these new synapses.

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“…A device that can meet these characteristics is the¯oating-gate MOSFET (FGMOSFET) (Ong et al 1989, Thomsen and Brooke 1991, Durfee and Shoucair 1992, Sim et al 1992). In the present paper, an analysis is made for using such a device in a bidirectional associative memory (BAM), calculating beforehand the correlation matrix for a 6 £ 3 array (as a heteroassociative memory), designed to store three orthogonal vector pairs with Kosko's dot product method (Kosko 1987(Kosko , 1988.…”

Section: Introductionmentioning

confidence: 99%

Performance analysis by simulation of floating-gate MOSFETs applied on a bidirectional associative memory architecture

Reyes-Barranca¹,

Moreno-Cadenas²,

Castañeda³

2001

International Journal of Electronics

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Floating-gate MOSFETs (FGMOSFETs) are devices that can be electrically programmable and have a non-volatile characteristic. This feature can be adopted to con® gure a basic cell performing as a variable resistance that can be applied in arti® cial neural networks as a synapse. Based on a simple model and considering the coupling coe cient of the structure as the gain of a voltage controlled voltage source, the electrical characteristics of a¯oating-gate MOSFET can be simulated in PSpice and an arti® cial neural net, such as the bidirectional associative memory (BAM), can be implemented. Therefore a performance analysis of the net may be done with diOE erent sets of threshold voltages for the FGMOSFETs con® gured as a CMOS inverter used as a synapse. The objective is to know pattern pairs in a bidirectional way. The result is a correlation matrix for the BAM as a function of an electrical parameter of the devices, which is directly related to the respective matrix calculated by the matrix dot product, using the method outlined by Kosko.

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Comparison of floating gate neural network memory cells in standard VLSI CMOS technology

Cited by 25 publications

References 21 publications

The Prospects for Analogue Neural VLSI

The Prospects for Analogue Neural VLSI

An MDAC synapse for analog neural networks

Performance analysis by simulation of floating-gate MOSFETs applied on a bidirectional associative memory architecture

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