Comparison Between the Noise Performance of Double- and Single-Gate InP-Based HEMTs

Vasallo, B. G.; Wichmann, Nicolas; Bollaert, S.; Roelens, Y.; Cappy, A.; González, T.; Pardo, D.; Matéos, J.

doi:10.1109/ted.2008.921982

Cited by 28 publications

(26 citation statements)

References 10 publications

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“…The authors in their recent work proposed a charge control model based on Pucel's noise theory [8][9][10] for the noise performance evaluation of a symmetric tied-gate InAlAs/InGaAs double-gate HEMT [11]. Superior noise performance was observed for the DG-HEMT as compared to the SG-HEMT in terms of lower noise resistance and lower Minimum Noise Figure. The analytical results thereby obtained for the operating frequency of 94 GHz and at a high drain voltage of 0.5V were observed to show good agreement with the ATLAS device simulation results [12] and the earlier reported Monte Carlo simulation and experimental results [1]. In that approach the effect of the gate-to-drain capacitance (C gd ) on the noise performance of the device was not taken into account.…”

Section: Introductionsupporting

confidence: 63%

“…A greater saturation region length leads to higher drain current and transconductance which in turn results in better RF and noise performance in terms of higher cutoff frequency and lower Minimum Noise Figure. In the previous work [7], the transfer characteristics (I dS vs V gs ) of 100 nm gate-length InAlAs/InGaAs singlegate (SG) and symmetric tied-geometry double-gate (DG) HEMT obtained using the analytical model were compared and found to agree well with the experimental measurements reported by Vasallo et.al. [2], thereby, proving the validity of the proposed model.…”

Section: Charge Control Modelsupporting

confidence: 53%

“…Lower value of C is observed for higher value of drain voltage which is attributed to the reduced correlation between the thermal noise induced drain noise current and gate noise current in the linear region. [1]. The increase in NF min and T min at low values of drain current occurs due to decrease in transconductance (g m ) which results in the increase in the drain noise coefficient (P) and also due to the reduction in the gate-source capacitance (C gs ) which leads to higher value of gate noise coefficient (R).…”

Section: Resultsmentioning

confidence: 99%

“…InAlAs/InGaAs double-gate HEMTs have proved to be the most promising candidates for the future ultra-high frequency and low-noise applications with the maximum frequency of oscillation (f max ) as high as 286 GHz and the extrinsic Minimum Noise Figure (NF min ) as low as 2.1 dB at the operating frequency of 94 GHz reported for the 100 nm gate-length device [1][2][3][4][5][6][7]. However, for improving the accuracy of microwave and millimeterwave circuit design, a comprehensive and accurate active device model is imperative.…”

Section: Introductionmentioning

confidence: 99%

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Gate-to-Drain Capacitance Dependent Model for Noise Performance Evaluation of InAlAs/InGaAs Double-gate HEMT

Bhattacharya¹,

Jogi²,

Gupta³

et al. 2013

JSTS:Journal of Semiconductor Technology and Science

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Abstract-In the present work, the effect of the gateto-drain capacitance (C gd ) on the noise performance of a symmetric tied-gate In 0.52 Al 0.48 As/In 0.53 Ga 0.47 As double-gate HEMT is studied using an accurate charge control based approach. An analytical expression for the gate-to-drain capacitance is obtained. In terms of the intrinsic noise sources and the admittance parameters (Y 11 and Y 21 which are obtained incorporating the effect of C gd ), the various noise performance parameters including the Minimum noise figure and the Minimum Noise Temperature are evaluated. The inclusion of gate-todrain capacitance is observed to cause significant reduction in the Minimum Noise figure and Minimum Noise Temperature especially at low values of drain voltage, thereby, predicting better noise performance for the device.

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Section: Introductionsupporting

confidence: 63%

Section: Charge Control Modelsupporting

confidence: 53%

Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Gate-to-Drain Capacitance Dependent Model for Noise Performance Evaluation of InAlAs/InGaAs Double-gate HEMT

Bhattacharya¹,

Jogi²,

Gupta³

et al. 2013

JSTS:Journal of Semiconductor Technology and Science

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“…To further improve their behavior, alternative solutions based on an evolution of the standard HEMT design have been proposed, as the double-gate (DG) HEMT, a HEMT with two gates placed on each side of the conducting InGaAs channel [2][3][4][5][6]. The progress of the DG-HEMT technology has allowed the design and fabrication of III-V velocity modulation transistors (VMTs) [7,8].…”

Section: Introductionmentioning

confidence: 99%

Monte Carlo Analysis of the Dynamic Behavior οf InAlAs/InGaAs Velocity Modulation Transistors: A Geometrical Optimization

et al. 2011

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The influence of the geometry on the dynamic behavior of InAlAs/InGaAs velocity modulation transistors is analyzed by means of a Monte Carlo simulator in order to optimize the performance of this new type of transistor. In velocity modulation transistors, based on the topology of a double-gate high electron mobility transistor, the source and drain electrodes are connected by two channels with different mobilities, and electrons are transferred between both of them by changing the gate voltages in differential mode. Consequently, the drain current is modulated while keeping the total carrier density constant, thus in principle avoiding capacitance charging/ discharging delays. However, the low values taken by the transconductance, as well as the high capacitance between the two gates in differential-mode operation, lead to a deficient dynamic performance. This behavior can be geometrically optimized by increasing the mobility difference between the two channels, by increasing the channel width and, mainly, by reducing the gate length, with a higher immunity to short channel effects than the traditional architectures.

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Sheet‐carrier density and I‐V analysis of In_0.7Ga_0.3As/InAs/In_0.7Ga_0.3As/InAs/In_0.7Ga_0.3As dual channel double gate HEMT for THz applications

Poornachandran¹,

Mohankumar²,

Kumar

et al. 2019

Int J Numerical Modelling

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This paper gives a comprehensive detail about an emerging InAs high electron mobility transistor (HEMT) technology with proper material combination making it suitable for low-power and high-frequency applications. Over the decade, various material combinations were adopted to improve the sheetcarrier density and frequency performances. In this work, we report the performance and optimization of 30-nm gate length InAs-based dual channel double gate (DCDG) HEMT for terahertz application. The dual channel is formed in the device due to the combination of five layers (In 0.7 Ga 0.3 As/InAs/In 0.7 Ga 0.3 As/ InAs/In 0.7 Ga 0.3 As) and thus provides a significant improvement in drain current and transconductance. Moreover, the gate scaling with optimized gate to drainside recess length of gate (L rd ) leads to reduced parasitic (C gg ) and tremendously increases the RF performance metrics f max and f T . For this device, high drain current of 2.203 mA/μm with peak transconductance of 4.77 mS/μm is observed. Further optimization of L rd results in peak f T of 810 GHz and f max of 900 GHz at a drain source voltage V ds = 0.5 V. These parameters empower a feasibility of the device for submillimeter as well as terahertz applications.

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Comparison Between the Noise Performance of Double- and Single-Gate InP-Based HEMTs

Cited by 28 publications

References 10 publications

Gate-to-Drain Capacitance Dependent Model for Noise Performance Evaluation of InAlAs/InGaAs Double-gate HEMT

Gate-to-Drain Capacitance Dependent Model for Noise Performance Evaluation of InAlAs/InGaAs Double-gate HEMT

Monte Carlo Analysis of the Dynamic Behavior οf InAlAs/InGaAs Velocity Modulation Transistors: A Geometrical Optimization

Sheet‐carrier density and I‐V analysis of In_0.7Ga_0.3As/InAs/In_0.7Ga_0.3As/InAs/In_0.7Ga_0.3As dual channel double gate HEMT for THz applications

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Comparison Between the Noise Performance of Double- and Single-Gate InP-Based HEMTs

Cited by 28 publications

References 10 publications

Gate-to-Drain Capacitance Dependent Model for Noise Performance Evaluation of InAlAs/InGaAs Double-gate HEMT

Gate-to-Drain Capacitance Dependent Model for Noise Performance Evaluation of InAlAs/InGaAs Double-gate HEMT

Monte Carlo Analysis of the Dynamic Behavior οf InAlAs/InGaAs Velocity Modulation Transistors: A Geometrical Optimization

Sheet‐carrier density and I‐V analysis of In0.7Ga0.3As/InAs/In0.7Ga0.3As/InAs/In0.7Ga0.3As dual channel double gate HEMT for THz applications

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Sheet‐carrier density and I‐V analysis of In_0.7Ga_0.3As/InAs/In_0.7Ga_0.3As/InAs/In_0.7Ga_0.3As dual channel double gate HEMT for THz applications