Comparison Between Array Multiplier and Vedic Multiplier

Abstract

One of the most important arithmetic unit in DSPs and microprocessors is multiplier. It is also a major source of power dissipation. To reduce the power dissipation of multipliers is the key to satisfy the overall budget of digital circuits. This paper analyses and compares array multiplier with vedic multiplier so that we can select a better multiplier design to perform multiplication of two numbers. The main objective of our work is to calculate and compare the total number of LUTs utilized by array and vedic multipliers. The designs are done using ISE Design Suit 14.4 tool and are simulated using Modelsim 10.0c (Student edition) simulator.