Comparison and Simulation of Analog and Digital Phase Locked Loop

Godave, Abhishek; Choudhari, Pranali; Jadhav, Anita

doi:10.1109/icccnt.2018.8494198

Cited by 13 publications

(3 citation statements)

References 1 publication

Supporting

Mentioning

Contrasting

Order By: Relevance

“…However, some authors compare few PLLs [17], do not perform an evaluation on different voltage levels in the power network [18], or do not consider wind speed scenarios [8]. In addition, other papers have compared PLLs in other applications [22,[24][25][26]. In summary, there are differences among PLL implementations that affect their behavior when estimating frequency, depending on factors such as location, voltage level or penetration of renewable energy, among others.…”

Section: Introductionmentioning

confidence: 99%

Comparison of Phase-Locked Loops Used for Frequency Measurements in a Low-Inertia Power Grid with Wind Generation

et al. 2022

View full text Add to dashboard Cite

The need for more precise frequency measurements in electric power systems is increasing because of the growing penetration of renewable energy and the subsequent reduction in inertia, which gives rise to more intense frequency fluctuations. Phase-locked loops (PLLs) are now more accurate and present faster dynamic responses, helping to implement primary frequency controllers for renewable generators connected to the grid through power electronics. However, there are differences among PLL implementations that affect their behavior when estimating frequency, depending on factors as location, voltage level, or penetration of renewable energy, among other things. How this affects the ability of PLL-based frequency controllers to adequately estimate the instantaneous mismatch between generation and demand, especially in low-inertia power systems, is still unclear, and constitutes an open research topic. This paper contributes to this research effort by presenting a comparative study of different PLL configurations in order to gain insight into their performance in different scenarios in a low-inertia power system with a high share of wind energy. Constant and variable wind speed scenarios are considered, and PLL behavior is assessed in terms of the absolute mean value and the root-mean-square value of the frequency error, and the absolute value of the frequency derivative error. The results show that the PLL behavior depends on the voltage level and the location, and it was found that the further away the PLL is from the source that controls the frequency, the more noise is produced, which impacts the quality of the frequency measurement.

show abstract

Section: Introductionmentioning

confidence: 99%

Comparison of Phase-Locked Loops Used for Frequency Measurements in a Low-Inertia Power Grid with Wind Generation

et al. 2022

View full text Add to dashboard Cite

show abstract

“…On the other hand, the digital PLL provides short locking time and strong robustness against process, voltage, and temperature (PVT) changes due to the lack of analogue components [4]. Digital PLL can benefit for the shorter locking time depends on their controller type such as SAR [5]. Because of their larger locking step, they can reach correct locking point faster compared to analogue PLL despite digital PLL suffers from limited resolution.…”

Section: Introductionmentioning

confidence: 99%

Comparison of System-Level Design Approaches on Different Types of Digitally-Controlled Ring-Oscillator

2021

View full text Add to dashboard Cite

This paper presents a comparative study between two different implementations of digitally-controlled-oscillators (DCOs), whcih is the DAC-based and the digital controller-based DCO in TSMC 65 nm CMOS technology. This paper focuses on ring-oscillator architectures due to their high stability against PVT. The DAC-based oscillator implements a differential architecture, and the digital controller-based architecture operates in a single-ended signal. The SFDR of the DAC-based DCO is 77.2 dBc and controller-based DCO is 56.8 dBc at 125 MHz offset. The Monte-Carlo simulation gives a deviation of 7.4% and 8.5% for the DAC-based and controller-based DCO, respectively. The phase noise performance of the DAC-based DCO and controller-based DCO is −78.9 dBc/Hz and −81.3 dBc/Hz at 1 MHz offset, respectively. The implementations are given and compared according to their performance based on post-layout simulation results.

show abstract

“…This study uses the PLL technique instead of using series active power filter in case of distorted voltage source. The PLL technique is used to extract only the source voltage fundamental component from the distorted source voltage waveform and then deliver this pure source voltage signal as an input signal to the SAPF control scheme, so no need to use additional series active power filter [13][14][15][16][17][18].…”

Section: Introductionmentioning

confidence: 99%

Source current harmonic mitigation of distorted voltage source by using shunt active power filter

Mahmoud¹,

Mamdouh²,

Khalil³

2020

IJECE

View full text Add to dashboard Cite

In this paper, three-phase, four-wire shunt active power filter (SAPF) is utilized to mitigate system harmonics of distorted voltage source for unbalanced and nonlinear loads. Basically, the source voltage should be pure sinusoidal waveform to get a good mitigation of source current harmonics. In this under study system, the source voltage is assumed to be harmonic distortion non-sinusoidal voltage source. The phase locked loop (PLL) control circuit is wielded for extracting the fundamental component of the distorted source voltage to use it as an input signal to the SAPF control. Another input signal to the SAPF is the distorted load current. The SAPF control system uses (p-q) theory to calculate the optimum instantaneous current to be injected by the SAPF to mitigate the source current harmonics even the source voltage is harmonic distorted. MATLAB/SIMULINK software package is utilized to simulate the system under study. The effect of SAPF is tested when it’s used with and without the PLL control circuit. The simulation results show that, the THD of source current when using the PLL control circuit is improved to comply with the harmonic limits given in the IEEE 519-1992 and IEC 61000-4-7 standards.

show abstract

Comparison and Simulation of Analog and Digital Phase Locked Loop

Cited by 13 publications

References 1 publication

Comparison of Phase-Locked Loops Used for Frequency Measurements in a Low-Inertia Power Grid with Wind Generation

Comparison of Phase-Locked Loops Used for Frequency Measurements in a Low-Inertia Power Grid with Wind Generation

Comparison of System-Level Design Approaches on Different Types of Digitally-Controlled Ring-Oscillator

Source current harmonic mitigation of distorted voltage source by using shunt active power filter

Contact Info

Product

Resources

About