Comparing RTL and behavioral design methodologies in the case of a 2M-transistor ATM shaper

Moussa, I.; Sugar, Z.; Suescun, R.; Diaz-Nava, M.; Pavesi, M.; Crudo, S.; Gazi, L.; Jerraya, A.A.

doi:10.1109/dac.1999.781384

“…Studies have shown that ESL reduces the design effort by 50% or more while attaining excellent performance results [33]. It has recently received significant attention, as the steady increase in hardware complexity has made it increasingly High level specification of hardware design (in C, C++, System C) Implementation in hardware description language (in VHDL, Verilog)…”

Section: Motivationmentioning

confidence: 99%

Certifying Loop Pipelining Transformations in Behavioral Synthesis

Puri¹

2000

2

0

View full text Add to dashboard Cite

Due to the rapidly increasing complexity in hardware designs and competitive time to market trends in the industry, there is an inherent need to move designs to a higher level of abstraction. Behavioral Synthesis is the process of automatically compiling such Electronic System Level (ESL) designs written in high-level languages such as C, C++ or SystemC into Register-Transfer Level (RTL) implementation in hardware description languages such as Verilog or VHDL. However, the adoption of this flow is dependent on designers' faith in the correctness of behavioral synthesis tools.Loop pipelining is a critical transformation employed in behavioral synthesis process, and ubiquitous in commercial and academic behavioral synthesis tools. It

show abstract

“…Studies have shown that ESL reduces the design effort by 50% or more while attaining excellent performance results [33]. It has recently received significant attention, as the steady increase in hardware complexity has made it increasingly High level specification of hardware design (in C, C++, System C) Implementation in hardware description language (in VHDL, Verilog)…”

Section: Motivationmentioning

confidence: 99%

Certifying Loop Pipelining Transformations in Behavioral Synthesis

Puri¹

0

View full text Add to dashboard Cite

Due to the rapidly increasing complexity in hardware designs and competitive time to market trends in the industry, there is an inherent need to move designs to a higher level of abstraction. Behavioral Synthesis is the process of automatically compiling such Electronic System Level (ESL) designs written in high-level languages such as C, C++ or SystemC into Register-Transfer Level (RTL) implementation in hardware description languages such as Verilog or VHDL. However, the adoption of this flow is dependent on designers' faith in the correctness of behavioral synthesis tools.Loop pipelining is a critical transformation employed in behavioral synthesis process, and ubiquitous in commercial and academic behavioral synthesis tools. It

show abstract

“…VHDL or Verilog), the Firm Core is described and synthesized for specific library and finally the Hard Core is described at the layout level. Because of the growing complexity of SoC designs [2], design reuse methodologies are known as the better way to bridge the gap between performance and time-to-market [15,13] with nowadays methodologies and tools. For IP integrators, the challenges consist in understanding all the specifications of existing blocks responding to his needs, and in testing and interface development [9,10].…”

Section: Introductionmentioning

confidence: 99%

Behavioral IP specification and integration framework for high-level design reuse

Pillement

¹

,

Chillet

²

,

Sentieys

³

Proceedings International Symposium on Quality Electronic Design

View full text Add to dashboard Cite

Specifying virtual components at the behavioral level appears as the most promising solution to achieve a real efficiency of design reuse. In this paper we propose a methodology to specify and use Behavioral Level IP (BL-IP). Thus, IP designer tasks are easier due to the unified representation offered by this level of abstraction. The genericity of a behavioral IP permits efficient optimizations and make application context adaptations a reality. We propose a unified framework to define an IP at the behavioral level and to tune a particular block according to designer needs. Therefore, we define the IP generator tool and the Universal High Level Synthesis concept.

show abstract

Comparing RTL and behavioral design methodologies in the case of a 2M-transistor ATM shaper

Cited by 5 publications

References 10 publications

Certifying Loop Pipelining Transformations in Behavioral Synthesis

Certifying Loop Pipelining Transformations in Behavioral Synthesis

Certifying Loop Pipelining Transformations in Behavioral Synthesis

Behavioral IP specification and integration framework for high-level design reuse

Contact Info

Product

Resources

About