Comparing program phase detection techniques

Dhodapkar, Ashutosh S.; Smith, James E.

doi:10.1109/micro.2003.1253197

Cited by 130 publications

(128 citation statements)

References 25 publications

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“…Balasubramonian et al [19] used cache miss rates, cycles per instruction (CPI), and branch frequency characteristics to detect changes in application characteristics for cache tuning, and found that these characteristics were effective for phase classification. Dhodapkar et al [20] found a relationship between phases and the phases' working sets, and concluded that phase changes could be detected by detecting changes in the working set. In this work, we use execution statistics obtained from the microprocessor's hardware performance counters for phase classification [21].…”

Section: Phase-based Tuning and Dtmmentioning

confidence: 99%

“…For each generation, TaPT uses the previous generation's Pareto optimal set as the current generation's initial archive (line 15). TaPT calculates the fitness of the configurations in each population and archive using Equations (2) and (3), and updates the current generation's archive with the non-dominated configurations (lines [17][18][19][20][21]. To maintain the size of P i 's archive at A size , TaPT discards the least fit configurations or adds the most fit configurations from the population (line 22).…”

Section: Tapt Characterization Algorithmmentioning

confidence: 99%

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TaPT: Temperature-Aware Dynamic Cache Optimization for Embedded Systems

Adegbija

Gordon‐Ross

2017

Computers

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Embedded systems have stringent design constraints, which has necessitated much prior research focus on optimizing energy consumption and/or performance. Since embedded systems typically have fewer cooling options, rising temperature, and thus temperature optimization, is an emergent concern. Most embedded systems only dissipate heat by passive convection, due to the absence of dedicated thermal management hardware mechanisms. The embedded system's temperature not only affects the system's reliability, but can also affect the performance, power, and cost. Thus, embedded systems require efficient thermal management techniques. However, thermal management can conflict with other optimization objectives, such as execution time and energy consumption. In this paper, we focus on managing the temperature using a synergy of cache optimization and dynamic frequency scaling, while also optimizing the execution time and energy consumption. This paper provides new insights on the impact of cache parameters on efficient temperature-aware cache tuning heuristics. In addition, we present temperature-aware phase-based tuning, TaPT, which determines Pareto optimal clock frequency and cache configurations for fine-grained execution time, energy, and temperature tradeoffs. TaPT enables autonomous system optimization and also allows designers to specify temperature constraints and optimization priorities. Experiments show that TaPT can effectively reduce execution time, energy, and temperature, while imposing minimal hardware overhead.

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Section: Phase-based Tuning and Dtmmentioning

confidence: 99%

Section: Tapt Characterization Algorithmmentioning

confidence: 99%

TaPT: Temperature-Aware Dynamic Cache Optimization for Embedded Systems

Adegbija

Gordon‐Ross

2017

Computers

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“…It examines the application's execution path to detect hardware independent phases [21,14]. Such phases can be readily missed by performance counter based phase detection, while changes in executed code reflect changes in many different metrics [20,21,5,22,9,18]. To leverage this, ScarPhase monitors what code is executed by dividing the application into windows and using hardware performance counters to sample which branches execute in a window.…”

Section: Phase Detectionmentioning

confidence: 99%

“…where c new_est is the new estimate, c est is the old estimate, BW est is the estimated bandwidth demand, BW m is the measured bandwidth received and finally, BW M AX is the maximum bandwidth our system can provide 5 . In other 5 We estimated the real-world bandwidth limit of our reference system to approximately 12 GB/s using the STREAM benchmark [13].…”

Section: Bandwidthmentioning

confidence: 99%

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Modeling performance variation due to cache sharing

Sandberg

Sembrant

Hägersten

et al. 2013

2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)

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Shared cache contention can cause significant variability in the performance of co-running applications from run to run. This variability arises from different overlappings of the applications' phases, which can be the result of offsets in application start times or other delays in the system. Understanding this variability is important for generating an accurate view of the expected impact of cache contention. However, variability effects are typically ignored due to the high overhead of modeling or simulating the many executions needed to expose them. This paper introduces a method for efficiently investigating the performance variability due to cache contention. Our method relies on input data captured from native execution of applications running in isolation and a fast, phaseaware, cache sharing performance model. This allows us to assess the performance interactions and bandwidth demands of co-running applications by quickly evaluating hundreds of overlappings.We evaluate our method on a contemporary multicore machine and show that performance and bandwidth demands can vary significantly across runs of the same set of co-running applications. We show that our method can predict application slowdown with an average relative error of 0.41% (maximum 1.8%) as well as bandwidth consumption. Using our method, we can estimate an application pair's performance variation 213× faster, on average, than native execution.

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Incorporating hardware and software features into a prediction model for processor‐system throughput

Beg

Prasad

2015

Comp Applic In Engineering

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ABSTRACT:The cycle-accurate simulation is a method for design space study of a processor system before it goes for the hardware implementation. Even though the simulations provide precise results about the system performance, the simulation times are exorbitantly high for practical systems. Therefore, an alternative is to use experimentally-developed models that tend to be faster than the aforementioned simulations. This is an extension to our previous work done in the area of neural network models for assessing the processor system throughput. In addition to hardware-related parameters, the current work includes multiple software-related parameters to better represent the dynamic behavior of programs. Consequently, the model provides higher accuracy estimates of a widely used performance metric (instructions per cycle) when tested with industry standard CPU benchmark programs. Potential uses of the model are compiler design and computer architecture research and teaching.

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Comparing program phase detection techniques

Abstract: Abstract

Cited by 130 publications

References 25 publications

TaPT: Temperature-Aware Dynamic Cache Optimization for Embedded Systems

TaPT: Temperature-Aware Dynamic Cache Optimization for Embedded Systems

Modeling performance variation due to cache sharing

Incorporating hardware and software features into a prediction model for processor‐system throughput

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