Comparator Design for Low Power High Speed Flash ADC-A Review

Chacko, Litty; Varghese, George Tom

doi:10.1109/iccmc.2019.8819762

Cited by 2 publications

(1 citation statement)

References 9 publications

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“…A lowpotential bulk-driven based latch comparator structure [16] is proposed, which incline the mass hubs concept and sufficient potentials in the testing stage to lower their edge voltages, while setting the input information into the mass hubs during the contrast process to provide additional transconductance. To eliminate the effect of the bubble fault, the Flash ADC [17] employs the offset-cancellation process. However, this approach is ineffective at high resolution.…”

Section: Related Workmentioning

confidence: 99%

Design and Analysis of 4-bit 1.2GS/s Low Power CMOS Clocked Flash ADC

Prathiba¹,

Santhi²

2022

Intelligent Automation &Amp; Soft Computing

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High-quality, high-resolution flash ADCs are used in reliable VLSI (Very Large-Scale Integrated) circuits to minimize the power consumption. An analogue electrical signal is converted into a discrete-valued sequence by these ADCs. This paper proposes a four-bit 1.2GS/s low-power Clocked Flash ADC (C-FADC). A low-power Clocked-Improved Threshold Inverter Quantization (CITIQ) comparator, an Adaptive Bubble Free (ABF) logic circuit, and a compact Binary Encoder (BE) are all part of the presented structure. A clock network in the comparator circuit reduces skew and jitters, while an ABF logic circuit detects and corrects fourth order bubble faults detected from thermometer code, and then the BE transforms the bubble free code into binary code. A Tanner EDA with 250-nm Technology is used to implement the C-FADC. The proposed design achieves ENOB of 3.56, uses 3.24 mW of power, and has a FOM of 0.274pJ/conv.-step at an input frequency of 85 MHz. The suggested C-FADC has differential and integral nonlinearities of ±0.65 LSB and +0.45/-0.5 LSB, respectively.

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Section: Related Workmentioning

confidence: 99%