Comparator Circuits over Finite Bounded Posets

Komarath, Balagopal; Sarma, Jayalal; Sunil, K.

doi:10.1016/j.ic.2018.02.002

Cited by 3 publications

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“…Can our results and techniques applied to comparator circuits be extended to those variations of comparator circuits? Can this extension shed any light into the classes characterised by [KSS18]?…”

Section: Directions and Open Problemsmentioning

confidence: 97%

“…Extensions and restrictions of comparator circuits. Recent work of Komarath, Sarma and Sunil [KSS18] has provided characterisations of various complexity classes, such as L, P and NP, by means of extensions or restrictions of comparator circuits. Can our results and techniques applied to comparator circuits be extended to those variations of comparator circuits?…”

Section: Directions and Open Problemsmentioning

confidence: 99%

“…We don't know if there is a linear-size comparator circuit for Majority 4 , whereas, for the weaker model of nondeterministic branching programs, superlinear lower bounds are known [Raz90]. Structural questions about comparator circuits have also received some attention in recent years [GKRS19,KSS18].…”

Section: Introductionmentioning

confidence: 99%

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Algorithms and Lower Bounds for Comparator Circuits from Shrinkage

Cavalar

2021

Preprint

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Comparator circuits are a natural circuit model for studying bounded fan-out computation whose power sits between nondeterministic branching programs and general circuits. Despite having been studied for nearly three decades, the first superlinear lower bound against comparator circuits was proved only recently by Gál and Robere (ITCS 2020), who established a Ω (n/ log n) 1.5 lower bound on the size of comparator circuits computing an explicit function of n bits.In this paper, we initiate the study of average-case complexity and circuit analysis algorithms for comparator circuits. Departing from previous approaches, we exploit the technique of shrinkage under random restrictions to obtain a variety of new results for this model. Among them, we show

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Section: Directions and Open Problemsmentioning

confidence: 97%

Section: Directions and Open Problemsmentioning

confidence: 99%

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Algorithms and Lower Bounds for Comparator Circuits from Shrinkage

Cavalar

2021

Preprint

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Algorithms and Lower Bounds for Comparator Circuits from Shrinkage

Cavalar

2023

Algorithmica

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In this paper, we initiate the study of average-case complexity and circuit analysis algorithms for comparator circuits. Departing from previous approaches, we exploit the technique of shrinkage under random restrictions to obtain a variety of new results for this model. Among them, we show Average-case Lower Bounds For every $$k = k(n)$$ k = k ( n ) with $$k \geqslant \log n$$ k ⩾ log n , there exists a polynomial-time computable function $$f_k$$ f k on n bits such that, for every comparator circuit C with at most $$n^{1.5}/O\!\left( k\cdot \sqrt{\log n}\right) $$ n 1.5 / O k · log n gates, we have $$\begin{aligned} \mathop {{{\,\mathrm{\textbf{Pr}}\,}}}\limits _{x\in \left\{ 0,1\right\} ^n}\left[ C(x)=f_k(x)\right] \leqslant \frac{1}{2} + \frac{1}{2^{\Omega (k)}}. \end{aligned}$$ Pr x ∈ 0 , 1 n C ( x ) = f k ( x ) ⩽ 1 2 + 1 2 Ω ( k ) . This average-case lower bound matches the worst-case lower bound of Gál and Robere by letting $$k=O\!\left( \log n\right) $$ k = O log n . $$\#$$ # SAT Algorithms There is an algorithm that counts the number of satisfying assignments of a given comparator circuit with at most $$n^{1.5}/O\!\left( k\cdot \sqrt{\log n}\right) $$ n 1.5 / O k · log n gates, in time $$2^{n-k}\cdot {{\,\textrm{poly}\,}}(n)$$ 2 n - k · poly ( n ) , for any $$k\leqslant n/4$$ k ⩽ n / 4 . The running time is non-trivial (i.e., $$2^n/n^{\omega (1)}$$ 2 n / n ω ( 1 ) ) when $$k=\omega (\log n)$$ k = ω ( log n ) . Pseudorandom Generators and $$\textsf {MCSP} $$ MCSP Lower Bounds There is a pseudorandom generator of seed length $$s^{2/3+o(1)}$$ s 2 / 3 + o ( 1 ) that fools comparator circuits with s gates. Also, using this PRG, we obtain an $$n^{1.5-o(1)}$$ n 1.5 - o ( 1 ) lower bound for $$\textsf {MCSP} $$ MCSP against comparator circuits.

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Algorithms and Lower Bounds for Comparator Circuits from Shrinkage

Cavalar,

2022

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Comparator Circuits over Finite Bounded Posets

Cited by 3 publications

References 3 publications

Algorithms and Lower Bounds for Comparator Circuits from Shrinkage

Algorithms and Lower Bounds for Comparator Circuits from Shrinkage

Algorithms and Lower Bounds for Comparator Circuits from Shrinkage

Algorithms and Lower Bounds for Comparator Circuits from Shrinkage

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