Comparative study of single Material gate and Dual Material gate Silicon-On-Insulator Junctionless Transistors

Wagaj, S. C.; Chavan, Y. V.

doi:10.1109/isco.2017.7855997

Cited by 2 publications

(1 citation statement)

References 15 publications

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“…Moreover, due to high channel doping the mobility reduces due to ionization scattering and subsequently results in lower transconductance [6] [7] . To overcome these challenges, many authors have introducing solutions such as junctionless nanowire transistor with a dual material gate [8] , dual material gate junctionless transistor with high-k spacer [9] , dual material gate silicon on nothing junctionless transistor [10] , dual material double gate junctionless transistor considering fringing field [11] , charge plasma based transistor with induced graded channel [12] , gate-all-around junctionless transistor [13] , non-uniformly doped symmetric double gate junctionless transistor [14] , have been proposed. Among these junctionless transistor and architecture, dual material double gate junctionless transistor is best candidate for CMOS logic circuits [15] .…”

Section: Introductionmentioning

confidence: 99%

Performance Analysis of CMOS Circuits using Shielded Channel Dual Gate Stack Silicon on Nothing Junctionless Transistor

Wagaj¹,

Patil²

2021

IJEAT

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In this paper it has been demonstrated that a shielded channel made by varying the side gate length in silicon-on-nothing junctionless transistor not only improves the short channel effect but also improve the performance of CMOS circuits of this device. The proposed device shielded channel dual gate stack silicon on nothing junctionless transistor (SCDGSSONJLT) drain induced barrier lowering (DIBL), cut-off frequency and subthreshold slope are improved by 20%, 39% and 20% respectively over the single material gate silicon on insulator junctionless transistor (SMG SOI JLT). The proposed device CMOS inverter fall time Tf (pS) and noise margin improves by 50% and 10% compare to shielded channel silicon on insulator junctionless transistor (SCSOIJLT). It has been observed that circuit simulation of CMOS inverter, NAND and NOR of proposed device. The static power dissipation in the case of proposed SCDGSSONJLT device are reduced by 45%, 81% and 83% respectively over the SMGSOIJLT. Thus, significant improvement in DIBL, cut-off frequency, propagation delay and static power dissipation at low power supply voltage shows that the proposed device is more suitable for low power CMOS circuits.

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