Comparative Study of Plasma Source-Dependent Charging Polarity in Metal–Oxide–Semiconductor Field Effect Transistors with High-k and SiO₂ Gate Dielectrics

Abstract

Friction is ubiquitous in all aspects of everyday life and has consequently been under study for centuries. Classical theories of friction have been developed and used to successfully solve numerous tribological problems. However, modern applications that involve advanced materials operating under extreme environments can lead to situations where classical theories of friction are insufficient to describe the physical responses of sliding interfaces. Here, we review integrated experimental and computational studies of atomic-scale friction and wear at solid-solid interfaces across length and time scales. The influence of structural orientation in the case of carbon nanotube bundles, and molecular orientation in the case of polymer films of polytetrafluoroethylene and polyethylene, on friction and wear are discussed. In addition, while friction in solids is generally considered to be athermal, under certain conditions thermally activated friction is observed for polymers, carbon nanotubes and graphite. The conditions under which these transitions occur, and their proposed origins, are discussed. Lastly, a discussion of future directions is presented.

TDDB lifetime enhancement of high-k MOSFETs damaged by plasma processing — Conflicting results in plasma charging damage evaluation

“…Owing to the effects of trapped charges in these relatively thicker high-k dielectrics, the stress current (J CVS ) of the damaged sample becomes smaller than that of no-damaged one. Thus, we speculate that this feature is induced by the effect of trapped charges during a CVS measurement [2,9]. Figs.…”

“…In the following, let us focus on the mechanism of the t CVS increase. It was reported [9] that the direction of V th in a high-k MOSFET depends on the amount of PCD. The number of created defects, the nature of trap sites, and the distribution of charge trapping sites determine this charging polarity.…”

“…In particular, it was pointed out [2,6] that the parameter variations of high-k MOSFETs built in an LSI may be enhanced by the distribution of interconnect lengths adopted in the circuit design called the Rent's rule [7,8]. Regarding high-k dielectrics, owing to characteristic charge trapping/detrapping mechanisms, it was also reported [9] that V th by PCD exhibits complicated behaviors, e.g., the direction of V th depends on the amount of PCD. In order to evaluate PCD to high-k MOSFETs accurately, and further optimize a circuit layout regarding the antenna design rules, the PCD should be identified from various aspects such as the performance and reliability parameters.…”

Effects of plasma-induced charging damage on random telegraph noise in metal–oxide–semiconductor field-effect transistors with SiO2 and high-k gate dielectrics

“…Pads with a constant area of 42000 µm 2 served as antennas of the box-type structure. 23,36,37) Figure 1 shows plasma charging damage to MOSFETs. As shown in Fig.…”

“…Recently, it has also been found that not only conventional MOSFETs with SiO 2 but also those with high-k films suffer from threshold voltage (V th ) shift induced by PCD. 23) The V th shift is mainly attributed to defects created by PCD in gate dielectrics and SiO 2 /Si interface states. Such created defects induce carrier trapping and detrapping.…”