Comparative Studies of Long-Term Ambiance and Electrical Stress Stability of IGZO Thin-Film Transistors Annealed Under Hydrogen and Nitrogen Ambiance

Negative threshold voltage shift in an a-IGZO thin film transistor under X-ray irradiation

“…26 On the other hand, another possible form of hydrogen, H i + , is movable even at room temperature and can be removed from the a-IGZO lm as H 2 molecules. 27 Therefore, the V TH shi even aer 70 days is likely associated with the H O + state. In addition, another interpretation for the Fig.…”

Control of O-H bonds at a-IGZO/SiO2 interface by long time thermal annealing for highly stable oxide TFT

“…[6][7][8][9][10][11] Therefore, there have been many studies on improving AOS TFT stability such as high-pressure oxygen annealing, 12 annealing in hydrogen environment, 13 O 2 plasma treatment, 14 suitable passivation materials, 15 long channel TFT 16 and long-time annealing, etc. 17 Especially, the performance of a-IGZO TFT depends on channel length, and the TFTs with channel length less than 2 µm exhibit mostly depletion mode behavior. 18,19 Hence, the annealing technique to make the transfer shift to the positive gate voltage (V G ) is significant.…”

Reliability-Aware SPICE Compatible Compact Modeling of IGZO Inverters on a Flexible Substrate

“…However, when Al 2 O 3 is deposited by low-temperature ALD, the AlO-H bonding tends to have weak bonding that can lead to a negative V T shift. This is known as a hydrogen migration phenomenon as a result of the movement of H + ions (Figure 2b,c) [18][19][20][21][22][23]. The movement of electrons and hydrogens when the positive voltage is applied to the gate electrode is represented in Figure 2b.…”

“…This is due to electron-trapping inside the gate insulator and on the interface trap. However, when the gate insulator is aluminum oxide (Al 2 O 3 ) deposited by atomic layer deposition (ALD) at low temperatures, in addition to electron-trapping that generates positive ∆V T , there is also a hydrogen migration mechanism that generates negative ∆V T [18][19][20][21][22][23]. Cho et al investigated the static and dynamic bias stress-induced charge trapping and de-trapping in IGZO TFTs [18].…”

“…Cho et al investigated the static and dynamic bias stress-induced charge trapping and de-trapping in IGZO TFTs [18]. On et al examined the impact of channel length on the performance of IGZO TFTs with self-aligned structures [19]. Although these studies investigated the mechanism of V T shift in various conditions, the studies were performed at the transistor level, which has a limitation in circuit-level AC simulation.…”