Comparative Investigation into Classical and Spiking Neuron Implementations on FPGAs

Spiking Neuron Networks (SNNs) are often referred to as the 3 rd generation of neural networks. Highly inspired from natural computing in the brain and recent advances in neurosciences, they derive their strength and interest from an accurate modeling of synaptic interactions between neurons, taking into account the time of spike firing. SNNs overcome the computational power of neural networks made of threshold or sigmoidal units. Based on dynamic event-driven processing, they open up new horizons for developing models with an exponential capacity of memorizing and a strong ability to fast adaptation. Today, the main challenge is to discover efficient learning rules that might take advantage of the specific features of SNNs while keeping the nice properties (general-purpose, easy-to-use, available simulators, etc.) of traditional connectionist models. This chapter relates the history of the "spiking neuron" in Section 1 and summarizes the most currently-in-use models of neurons and synaptic plasticity in Section 2. The computational power of SNNs is addressed in Section 3 and the problem of learning in networks of spiking neurons is tackled in Section 4, with insights into the tracks currently explored for solving it. Finally, Section 5 discusses application domains, implementation issues and proposes several simulation frameworks.

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“…Several chapters in [99] are dedicated to this subject, and more recent work can be found for instance in [170,53,77,33,125,116,150].…”

Section: Implementing Snnsmentioning

confidence: 99%

Computing with Spiking Neuron Networks

Paugam-Moisy

Bohté

2012

Handbook of Natural Computing

202

114

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“…A standard design flow for FPGAs is used to implement neural networks in [7], where simple neural networks are evaluated in MATLAB first, and then synthesised to an FPGA with the Xilinx System Generator. The implemented LIF neuron model uses adders for summing incoming weighted pulses and an additional subtractor, which subtracts a shifted version of the membrane potential from the membrane potential at each time step.…”

Section: Related Workmentioning

confidence: 99%

A Digital Framework for Pulse Coded Neural Network Hardware with Bit-Serial Operation

Kaulmann

Dikmen

Rückert

2007

7th International Conference on Hybrid Intelligent Systems (HIS 2007)

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“…In order to investigate pulse transmission errors both conventional interconnect and the TMA were used to interconnect neuron layers in a SNN topology that has been pre trained to solve the benchmark XOR problem [10]. Both topologies were simulated using the XSG toolset from Xilinx [11], as illustrated in figure 4.…”

Section: Xilinx System Generator Implementationmentioning

confidence: 99%

“…Both topologies were simulated using the XSG toolset from Xilinx [11], as illustrated in figure 4. The SNN was trained off-line by an Evolutionary Strategy (ES) [10]. Table 1 shows three input neurons where neuron 1 is a biasing neuron [10], which fires at 0ms, and neurons 2 and 3 provide the conventional 2 inputs for the XOR truth table.…”

Section: Xilinx System Generator Implementationmentioning

confidence: 99%

“…The SNN was trained off-line by an Evolutionary Strategy (ES) [10]. Table 1 shows three input neurons where neuron 1 is a biasing neuron [10], which fires at 0ms, and neurons 2 and 3 provide the conventional 2 inputs for the XOR truth table. Note that column four is the post-trained firing times of the output neuron where the simulation used conventional metal interconnect.…”

Section: Xilinx System Generator Implementationmentioning

confidence: 99%

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A Time Multiplexing Architecture for Inter-neuron Communications

Tuffy

McDaid

McGinnity

et al. 2006

Artificial Neural Networks – ICANN 2006

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Abstract. This paper presents a hardware implementation of a Time Multiplexing Architecture (TMA) that can interconnect arrays of neurons in an Artificial Neural Network (ANN) using a single metal wire. The approach exploits the relative slow operational speed of the biological system by using fast digital hardware to sequentially sample neurons in a layer and transmit the associated spikes to neurons in other layers. The motivation for this work is to develop minimal area inter-neuron communication hardware. An estimate of the density of on-chip neurons afforded by this approach is presented. The paper verifies the operation of the TMA and investigates pulse transmission errors as a function of the sampling rate. Simulations using the Xilinx System Generator (XSG) package demonstrate that the effect of these errors on the performance of an SNN, pre-trained to solve the XOR problem, is negligible if the sampling frequency is sufficiently high.

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Comparative Investigation into Classical and Spiking Neuron Implementations on FPGAs

Cited by 15 publications

References 3 publications

Computing with Spiking Neuron Networks

Computing with Spiking Neuron Networks

A Digital Framework for Pulse Coded Neural Network Hardware with Bit-Serial Operation

A Time Multiplexing Architecture for Inter-neuron Communications

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