Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems

Abstract

In this paper, we propose a set of rules for consistent estimation of the real performance and power features of the flip-flop and master-slave latch structures. A new simulation and optimization approach is presented, targeting both highperformance and power budget issues. The analysis approach reveals the sources of performance and power-consumption bottlenecks in different design styles. Certain misleading parameters have been properly modified and weighted to reflect the real properties of the compared structures. Furthermore, the results of the comparison of representative master-slave latches and flipflops illustrate the advantages of our approach and the suitability of different design styles for high-performance and low-power applications.

Design and Analysis of Dual Edge Triggered (DET) Flip-Flops Using Multiple C-Elements

“…Post-layout simulations showed that the kit's estimates for small designs are often conservative and that compact circuits often perform slightly faster in post-layout simulations than in schematic simulations with the automatic parasitic network estimation turned on. The simulation test bench that is used in this comparison is very similar to the ones used in [5], [13], [14]. The Q output of a simulated flip-flop is connected to a load of four symmetric inverters with their n-type transistors sized at minimum recommended width.…”

Selective Clock-Gating for Low Power/Low Noise Synchronous Counters

“…To implement it, a modular design has been developed based on the cell in Fig 1b. The circuit has been designed using the AMS standard 0.35 µm CMOS library. Although power consumption and noise generation strongly depends on the kind of flip-flops used [6,7] our goal is to explore what improvements can be done in a counter with a given flip-flop.…”

Modeling and Characterizing Power Variability in Multicore Architectures

“…At present, we have layout/circuit models for a simple dual bitline SRAM cell, a multi-ported (4r,2w) SRAM cell, a simple CAM cell, an ALU bit slice, and a pipeline latch comparable to one used in the PowerPC 603 [32]. As we continue the development of VariPower, we hope to extend this list to cover more circuits.…”