Compact Switched-Capacitor Power Detector With Frequency Compensation in 65-nm CMOS

Abstract

This work presents a compact switched-capacitor power detector (PD) with frequency compensation technique in a 65-nm CMOS process. Utilizing self-biased MOSFET as switches, the PD works both at the positive and the negative cycle to increase the dynamic range (DR). The output of traditional power detectors usually change with the variations of input frequencies which make the measurement of PD more difficult. In this design, by adding a feed-forward frequency detection circuit, the load resistors of the power detector are changed according to the input frequencies. Thus, the effect of input frequency variation is minimized. The measured operation frequency of the power detector is from 3 GHz to 5 GHz with a dynamic range of 20 dB with an error of ±2 dB. The variations of the output voltage are reduced from more than 4 dB to ±0.5 dB, achieving a variation of less than ±0.25 dB/GHz. To the authors' knowledge, it is the first power detector with input frequency compensation. The core of the power detector occupies an area of 0.014 mm 2 and consumes 2.04 mW static power. INDEX TERMS CMOS power detector, dynamic range, frequency compensation, self-biased MOSFET.