Compact Modeling of Negative Capacitance Nanosheet FET including Quasi-Ballistic Transport

Gaidhane, Amol D.; Pahwa, Girish; DasGupta, Anirvan; Verma, Amit; Chauhan, Yogesh Singh

doi:10.1109/edtm47692.2020.9117841

Cited by 3 publications

(2 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…They considered radial dependence of the electric field in the ferroelectric materials, which had been ignored in previous works, and accurately captured ferroelectric material parameter variation in the non-hysteresis regime [105]. In 2020, A. D. Gaidhane quasi ballistic transport exacerbated the capacitance matching in NC GAA-FET compared to that in the drift-diffusion only case [106]. In 2021, Jongwook Jeon et al proposed a compact model of NC GAA-FET describing current-voltage (I-V) with interface trap effects considered for the first time, and the proposed model showed good alignment with the results of implicit numerical calculations [107].…”

Section: A Simulation Status Of Nc Gaa-fetmentioning

confidence: 99%

Recent Developments in Negative Capacitance Gate-All-Around Field Effect Transistors: A Review

Qin

Wei

et al. 2023

IEEE Access

View full text Add to dashboard Cite

With transistors scaling down to 3 nm node and beyond, short channel effect (SCE) as well as power consumption dissipation present immense challenges for further scaling down of the transistor. Hence the Gate all around field effect transistor (GAA-FET) is proposed to replace the Fin field effect transistor (FinFET) in 3 nm technology node and beyond due to its better gate control over the channel with surrounding gate structure, thus providing improved SCE constraint ability. Traditional transistors suffer from the problems of "Boltzmann Tyranny" and cannot overcome the subthreshold swing (SS) limit of 60 mV/dec at room temperature. To maintain high Ion and avoid Ioff from increasing too much, supply voltage (VDD) of the conventional transistor cannot scale down proportionally with the dimension of the transistor. The concept of negative capacitance (NC) has been demonstrated to be able to obtain sub-60 mV/dec SS with the ability of amplifying the potential of the channel region without VDD increment. The novel device structure of negative capacitance gate all around field effect transistor ( NC GAA-FET) can combine both the advantages of GAA-FET and NC-FET, and is the most promising ultra-low power consumption device and promises to sustain the Moore's law further beyond what is predicted now. Whereas, according to our knowledge, there have been few review papers about NC GAA-FET till now. Herein, we summarize the recent advances of the NC GAA-FET both in simulation and experimental aspects, which we believe will bring about profound changes to the further development of NC GAA-FET devices.INDEX TERMS Negative capacitance effect, short channel effect, subthreshold swing, power consumption dissipation, negative capacitance gate all around field effect transistor.

show abstract

Section: A Simulation Status Of Nc Gaa-fetmentioning

confidence: 99%

Recent Developments in Negative Capacitance Gate-All-Around Field Effect Transistors: A Review

Qin

Wei

et al. 2023

IEEE Access

View full text Add to dashboard Cite

show abstract

“…We include the drift diffusive as well as ballistic transport in our model, which is inevitable at such small dimensions [11]. In addition to our previous work [12], we develop a terminal charge model in this paper using the core model and inner fringing charge model, which is based on the capacitive network approach [8].…”

Section: Introductionmentioning

confidence: 99%

Compact Modeling of Surface Potential, Drain Current and Terminal Charges in Negative Capacitance Nanosheet FET including Quasi-Ballistic Transport

Gaidhane

Pahwa

DasGupta

et al. 2020

IEEE J. Electron Devices Soc.

View full text Add to dashboard Cite

In this paper, we propose a compact model for Negative Capacitance Nanosheet Field Effect Transistor (NC-NSFET) including quasi-ballistic transport for sub-7nm technology node. The model captures the electrical characteristics of NC-NSFET for different ferroelectric thicknesses. Further, it captures the reverse short channel effects of NCFET for different channel lengths with a single set of parameters. Also, we build a model for terminal charges of NC-NSFET using the core model and the earlier developed inner fringing charge model. Using our physicsbased model, we find that quasi ballistic transport worsens the capacitance matching in NCFET compared to drift-diffusion only case. We validate the compact model for the drain current and the terminal charges with the TCAD results. The proposed compact model is computationally efficient and implemented in the Verilog-A code to enable SPICE circuit simulations. Finally, we demonstrate this by applying our model for NC-NSFET based CMOS inverter and SRAM circuit implementations in SPICE.

show abstract

Gate Engineered Ferroelectric Junctionless BioFET for Label-Free Detection of Biomolecules

Yadav,

Rewari,

Pandey

2023

J. Electron. Mater.

View full text Add to dashboard Cite

Compact Modeling of Negative Capacitance Nanosheet FET including Quasi-Ballistic Transport

Cited by 3 publications

References 6 publications

Recent Developments in Negative Capacitance Gate-All-Around Field Effect Transistors: A Review

Recent Developments in Negative Capacitance Gate-All-Around Field Effect Transistors: A Review

Compact Modeling of Surface Potential, Drain Current and Terminal Charges in Negative Capacitance Nanosheet FET including Quasi-Ballistic Transport

Gate Engineered Ferroelectric Junctionless BioFET for Label-Free Detection of Biomolecules

Contact Info

Product

Resources

About