Compact Implementation and Performance Evaluation of Hash Functions in ATtiny Devices

Abstract

Abstract. The pervasive diffusion of electronic devices in security and privacy sensitive applications has boosted research in cryptography. In this context, the study of lightweight algorithms has been a very active direction over the last years. In general, symmetric cryptographic primitives are good candidates for low-cost implementations. For example, several previous works have investigated the performance of block ciphers on various platforms. Motivated by the recent SHA3 competition, this paper extends these studies to another family of cryptographic primitives, namely hash functions. We implemented different algorithms on an ATMEL AVR ATtiny45 8-bit microcontroller, and provide their performance evaluation. All the implementations were carried out with the goal of minimizing the code size and memory utilization, and are evaluated using a common interface. As part of our contribution, we make all the corresponding source codes available on a web page, under an open-source license. We hope that this paper provides a good basis for researchers and embedded system designers who need to include more and more functionalities in next generation smart devices.

Secure PRNG seeding on commercial off-the-shelf microcontrollers

“…Instead, we base our recommendations on Balasch et al [2], in which a wide selection of 25 different hash functions, written in hand-optimized assembly, are presented. The implementations in [2] are for an 8-bit Atmel AVR chip, and thus not directly transferable to the chips that we have investigated. However, the required code sizes can be used as a relative size indicator.…”

“…Table 3 clearly shows that the STM32F100R8 microcontroller has plenty entropy left over in its SRAM pattern for Table 3: Hash function SRAM requirements and influence on SRAM entropy in STM32F100R8 (8 KiB SRAM). SRAM consumption data from [2]. Remaining min-entropy based on a pessimistic min-entropy estimate of 3% (see Section 3.3).…”

“…Assuming a required hash digest size of 256 bit, as required for FIPS 140-3 [15] compliance, the hash function, of those presented in [2], that requires the least storage is S-Quark, with 69 bytes. An alternative is PHOTON-256/32/32, which requires 82 bytes.…”

An Evaluation of Lightweight Block Ciphers for Resource-Constrained Applications: Area, Performance, and Security

“…Targeting usage of LWCs in automotive industries [6] surveyed the same in terms of hardware area (gate equivalent), energy consumption and latency while in [7] analyzes various LWCs with respect to energy as metric. Using ATMEL AVR ATtiny45 8-bit microcontroller as common platform performance of different LWCs have been evaluated w.r.t RAM usage, code size and cycle count for smart devices in [8]. In [9], side-channel resistance of lightweight weight block ciphers has been studied concerning software implementations, while [10] discusses mistakes in IEEE standard P1735 itself that allows successful launch of attack vectors to recover plaintext.…”

Evaluation of Secure Multi-Hop Node Authentication and Key Establishment Mechanisms for Wireless Sensor Networks

“…Implementation on sensor nodes is very hardware-dependent; optimization can be done for certain functions depending on the capacities and the design of the hardware. Thus comparing different implementations on different motes is not really conclusive, as is shown in [30][31][32][33]. The same applies for comparison by simulation, which is even less conclusive because simulation does not give an idea about how complex the operations are.…”