Compact Heterogeneous Integration for Next Generation High Frequency Scalable Array with Miniaturized and Efficient Power Delivery Network

Aslam, Shah Zaib; Ebrahimi, Najme

doi:10.48550/arxiv.2111.04567

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■ Electronic−photonic Co-packaging1

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2022

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“…2D Integration: This approach involves the EIC and PIC being connected on a printed circuit board (PCB) through a wire-bonding or flip-chip assembly process, which incites parasitic inductances and capacitances into the link between the EIC and PIC. 99 This integration approach also limits the shoreline density of edge electrical I/Os where the EICs and PICs can be interconnected, restricting its scalability. A 2D transceiver assembly on an electro-optical printed circuit board (EOCB) has been shown to operate at 50 Gb/s per channel.…”

Section: ■ Electronic−photonic Co-packagingmentioning

confidence: 99%

Integrated Photonics Packaging: Challenges and Opportunities

et al. 2022

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Packaging of photonic integrated circuit (PIC) chips is an essential and critical step before they can be integrated into functional optoelectronic systems. Photonic packaging is however often a major barrier impeding scalable deployment of PIC technologies given its high cost and limited throughput. This perspective addresses the technical challenges and discusses promising strategies and research directions to overcome the "packaging bottleneck".

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Section: ■ Electronic−photonic Co-packagingmentioning

confidence: 99%