Compact FPGA-based true and pseudo random number generators

Tsoi, Kuen Hung; Leung, Kim Hung; Leong, Philip H. W.

doi:10.1109/fpga.2003.1227241

Cited by 85 publications

(41 citation statements)

References 11 publications

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“…Generation methods can be different in principal and have different time of generation, generation pattern and repeatability [2]. Every application requires specific property of the RNG.…”

Section: Random Number Generationmentioning

confidence: 99%

A BBS Random Number Generator for Low Power Applications

Hassanzadeh¹,

Mahboubi²

2015

IJCA

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In this paper a low power random number generator has been designed and implemented using BBS algorithm. The BBS random number generator is known for high statistical quality and power consumption. Dynamic power dissipation has been reduced significantly comparing to regular implementation. Low power techniques such as power gating and pipelining have been employed to reduce power consumption of the module. Experimental measurements for a 32-bit BBS random number generator shows at least 30% reduction in dynamic power consumption. The proposed low power BBS random number generator has been implemented on Xilinx Spartan-6 FPGA evaluation board.

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“…Generation methods can be different in principal and have different time of generation, generation pattern and repeatability [2]. Every application requires specific property of the RNG.…”

Section: Random Number Generationmentioning

confidence: 99%

A BBS Random Number Generator for Low Power Applications

Hassanzadeh¹,

Mahboubi²

2015

IJCA

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“…Tsoi et al [2] evaluated an oscillator-sampling TRNG with a Xilinx Virtex FPGA device, and reported that the TRNG successfully passed NIST test [3], [4] at 5-29 kbps of generation rate. Since an oscillator-sampling TRNG requires two independent clock signals, Tsoi et al [2] connected external parts (two resistors and one capacitor) to the FPGA device. Meanwhile, this study presents a TRNG of fully synchronous digital circuit, which does not use any external parts.…”

Section: Related Studiesmentioning

confidence: 99%

FPGA Implementation of Metastability-Based True Random Number Generator

Hata

Ichikawa

2012

IEICE Trans. Inf. & Syst.

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SUMMARYTrue random number generators (TRNGs) are important as a basis for computer security. Though there are some TRNGs composed of analog circuit, the use of digital circuits is desired for the application of TRNGs to logic LSIs. Some of the digital TRNGs utilize jitter in freerunning ring oscillators as a source of entropy, which consume large power. Another type of TRNG exploits the metastability of a latch to generate entropy. Although this kind of TRNG has been mostly implemented with fullcustom LSI technology, this study presents an implementation based on common FPGA technology. Our TRNG is comprised of logic gates only, and can be integrated in any kind of logic LSI. The RS latch in our TRNG is implemented as a hard-macro to guarantee the quality of randomness by minimizing the signal skew and load imbalance of internal nodes. To improve the quality and throughput, the output of 64-256 latches are XOR'ed. The derived design was verified on a Xilinx Virtex-4 FPGA (XC4VFX20), and passed NIST statistical test suite without post-processing. Our TRNG with 256 latches occupies 580 slices, while achieving 12.5 Mbps throughput.

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“…Random numbers are also used for key generation in symmetric. For example, in the Smart cards, the main problem is the security which improves by using reliable random number generators (RNGs) [3].…”

Section: Introductionmentioning

confidence: 99%

Cryptographic PRNG Based on Combination of LFSR and Chaotic Logistic Map

Rahimov¹,

Babaei²,

Farhadi³

2011

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The random sequence generated by linear feedback shift register can't meet the demand of unpredictability for secure paradigms. A combination logistic chaotic equation improves the linear property of LFSR and constructs a novel random sequence generator with longer period and complex architecture. We present the detailed result of the statistical testing on generated bit sequences, done by very strict tests of randomness: the NIST suite tests, to detect the specific characteristic expected of truly random sequences. The results of NIST's statistical tests show that our proposed method for generating random numbers has more efficient performance.

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Compact FPGA-based true and pseudo random number generators

Cited by 85 publications

References 11 publications

A BBS Random Number Generator for Low Power Applications

A BBS Random Number Generator for Low Power Applications

FPGA Implementation of Metastability-Based True Random Number Generator

Cryptographic PRNG Based on Combination of LFSR and Chaotic Logistic Map

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