Compact and unified hardware architecture for SHA-1 and SHA-256 of trusted mobile computing

Kim, Mooseop; Lee, Deok Gyu; Ryou, Jae-Cheol

doi:10.1007/s00779-012-0543-0

Cited by 8 publications

(10 citation statements)

References 12 publications

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“…It is worth noting that the Padding Unit modifies only the last block of a message, leaving the others untouched. Since padding can be performed in software quite efficiently, without affecting the overall security of the system, many implementations [1], [76], [79], [80], [84], [85], [92], [93], [96]- [99] do not include the Padding Unit. These implementations take in already formatted PDBs.…”

Section: ) General Architecturementioning

confidence: 99%

“…Possible improvements rely on special devices for implementing the shift register, such as block RAMs (BRAMs) or first-in, first-out memory queue (FIFO)s [85], or the shift register mode of the configurable logic blocks (CLBs) of Xilinx R FPGAs [81]. A folded implementation of the Expander, employing only one adder, is proposed instead in [78], [79]. The unrolled implementation of the Expander is presented in [91], [95].…”

Section: ) General Architecturementioning

confidence: 99%

“…The whole circuit requires 490 clock cycles to fully compute a hash, hence effectively trading throughput for area and power consumption. The multi-mode extension of this architecture is presented in [79].…”

Section: B Shift Register Architecturesmentioning

confidence: 99%

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SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey

Martino

Cilardo

2020

IEEE Access

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While SHA-2 is a ubiquitous cryptographic hashing primitive, its role in emerging application domains, e.g. blockchains or trusted IoT components, has made the acceleration of SHA-2 very challenging due to new stringent classes of requirements, especially implementation cost and energy efficiency. The survey discusses these emerging applications and their fundamental requirements. Then, the work presents a comprehensive review of the different design techniques available in the literature for SHA-2 acceleration. The main focus of the presentation is placed on the impact of each design technique on the area, energy, power, and performance of the resulting accelerator, guiding the designer through the identification of the appropriate technique mixes which meet the constraints of any given application.

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Section: ) General Architecturementioning

confidence: 99%

Section: ) General Architecturementioning

confidence: 99%

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SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey

Martino

Cilardo

2020

IEEE Access

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“…When a node nk receives this packet, it can use PKp to verify the authenticity of OWHk0 and forwards the packet to the next node if the verification is passed. An elliptic curve public key scheme is implemented [11] on Berkeley motes and the cost is relatively low to perform one encryption or decryption process. To some extent, the public key approach is slow.…”

Section: Key Management Services For Lsddmentioning

confidence: 99%

“…A LSDD interest packet involves interest , blacklist , HMAC output of the packet, and the key of HMAC. We adopt SHA-1 [11] as HMAC function and key length is 32 bits (4 bytes). The output size of HMAC of SHA-1 is 20 bytes.…”

Section: Simulation and Performance Analysismentioning

confidence: 99%

Lightweight Secure Directed Diffusion for Wireless Sensor Networks

Wang

2014

International Journal of Distributed Sensor Networks

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A High-Efficiency FPGA-Based Multimode SHA-2 Accelerator

Pham

Tran

et al. 2022

IEEE Access

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The secure hash algorithm 2 (SHA-2) family, including the SHA-224/256/384/512 hash functions, is widely adopted in many modern domains, ranging from Internet of Things devices to cryptocurrency. SHA-2 functions are often implemented on hardware to optimize performance and power. In addition to the high-performance and low-cost requirements, the hardware for SHA-2 must be highly flexible for many applications. This paper proposes an SHA-2 hardware architecture named the multimode SHA-2 accelerator (MSA), which has high performance and flexibility at the system-on-chip level. To achieve high performance and flexibility, our accelerator applies three optimal techniques. First, a multimode processing element architecture is proposed to enable the accelerator to compute various SHA-2 functions for many applications. Second, a three-stage arithmetic logic unit pipeline architecture is proposed to reduce the critical paths and hardware resources. Finally, nonce generator and nonce validator architectures are proposed to reduce memory access and maximize the performance of the proposed MSA for blockchain mining applications. The MSA accuracy is tested on a real hardware platform (the Xilinx Alveo U280 FPGA). The experimental results on the field programmable gate array (FPGA) prove that the proposed MSA achieves significantly better performance, hardware efficiency, and flexibility than previous works. The evaluation results for energy efficiency show that the proposed MSA achieves up to 38.05 Mhps/W, which is 543.6 and 29 times better than the state-of-the-art Intel i9-10940X CPU and RTX 3090 GPU, respectively.INDEX TERMS SHA-2, blockchain mining, FPGA, multimode, Bitcoin, accelerator.

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Compact and unified hardware architecture for SHA-1 and SHA-256 of trusted mobile computing

Cited by 8 publications

References 12 publications

SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey

SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey

Lightweight Secure Directed Diffusion for Wireless Sensor Networks

A High-Efficiency FPGA-Based Multimode SHA-2 Accelerator

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