Compact and high‐throughput parameterisable architectures for memory‐based FFT algorithms

Abstract

Designers must carefully choose the best-suited fast Fourier transform (FFT) algorithm among various available techniques for the custom implementation that meets their design requirements, such as throughput, latency, and area. This article, to the best of authors' knowledge, is the first to present a compact and yet high-throughput parameterisable hardware architecture for implementing different FFT algorithms, including radix-2, radix-4, radix-8, mixed-radix, and split-radix algorithms. The designed architectures are fully parameterisable to support a variety of transform lengths and variable word-lengths. The FFT algorithms have been modelled and simulated in double-precision floating-point and fixed-point representations using authors' custom-developed library of numerical operations. The designed FFT architectures are modelled in Verilog hardware description language and their cycle-accurate and bit-true simulation results are verified against their fixed-point simulation models. The characteristics and implementation results of various FFT architectures on a Xilinx Virtex-7 FPGA are presented. Compared to recently published works, authors' memory-based FFT architectures utilise less reconfigurable resources while maintaining comparable or higher operating frequencies. The ASIC implementation results in a standard 45-nm CMOS technology are also presented for the designed memory-based FFT architectures. The execution times of FFTs on a workstation and a graphics processing unit are compared against authors' FPGA implementations.

Design of Spectrum Processing Chiplet Based on FFT Algorithm

“…According to the formula above, the DFT calculation of discrete sequence x ( n ) at N points is to obtain the corresponding value of X ( k ) in the frequency domain by summing the product of sequence x ( n ) and rotation factor . FFT is to continuously decompose the DFT of long sequence operators into the short sequence operators according to the periodicity and symmetry of rotation factor W , so as to reduce the amount of computation at each stage [ 15 ].…”

Memory-Based Self-Ordering FFT for Efficient I/O Scheduling

“…Some researchers prefer pipeline FFT architectures to perform continuous data flow and high speed [1,[3][4][5]15]. Other researchers employ memory-based FFT architectures because of the lower resource requirements and lesser occupied chip area [6,12,14,19]. Low resource and low power usage is especially important for hand-held battery powered devices.…”

“…Researchers try to improve performance by improving parallelism (reading/writing larger chunks, higher radix FFT) by proposing various memory addressing schemas, by efficient data feed-in/out to/from this structure and/or by reducing the resource (memory, chip area etc.) requirements [11,17,19]. The studies of Xiao et al [20,21] improved the address generation logic that has critical path independent of the transform size, hence suggested for large transforms by the authors.…”

The positive effect of the propaganda of family ethics and family education based on big data technology on the ideological work of youth

“…Big data computing models, i.e., various abstractions or models distilled and built from the diversity of big data computing problems and requirements according to the different data characteristics and computing features of big data [18][19][20][21][22]. Traditional parallel algorithms define more underlying models mainly at the programming language and architecture levels, big data processing requires more consideration of higher-level computational models in conjunction with these high-level features [23][24][25].…”