Compact and Energy Efficient Neuron With Tunable Spiking Frequency in 22-nm FDSOI

Eslahi, Hossein; Hamilton, Tara Julia; Khandelwal, Sourabh

doi:10.1109/tnano.2022.3157585

Cited by 7 publications

(4 citation statements)

References 54 publications

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“…However, the realisation of efficient SNN models in hardware require compact and energy efficient circuits which can be scaled towards large scale applications. Several CMOS based neuron circuits have been reported in recent years wherein a single neuron circuit has been implemented using multiple transistors and capacitors with additional bias lines [14]- [17]. These CMOS based designs suffer from lack of area efficiency and requires additional overhead circuitry.…”

Section: Introductionmentioning

confidence: 99%

Optimization of Leaky Integrate-and-Fire Neuron Circuits Based on Nanoporous Graphene Memristors

Mohanan,

Sattari-Esfahlan,

Cho

et al. 2024

IEEE J. Electron Devices Soc.

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Artificial neurons form the core of neuromorphic computing which is emerging as an alternative for the von Neumann computing architecture. However, existing neuron architectures still lack in area efficiency, especially considering the huge size of modern neural networks requiring millions of neurons. Here, we report on a compact leaky integrate and fire (LIF) neuron circuit based on graphene memristor device. The LIF circuit exhibits various biological properties like threshold control, leaky integration and reset behavior. Circuit parameters like the synaptic resistance and membrane capacitance act as additional control parameters whereby the spike frequency of the circuit can be effectively controlled. Uniquely, the circuit exhibits biologically realistic frequencies as low as 286 Hz. The results suggest the suitability of this compact and biorealistic LIF neuron circuit towards future bioinspired computing systems

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Section: Introductionmentioning

confidence: 99%

Optimization of Leaky Integrate-and-Fire Neuron Circuits Based on Nanoporous Graphene Memristors

Mohanan,

Sattari-Esfahlan,

Cho

et al. 2024

IEEE J. Electron Devices Soc.

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“…Further study on how to apply a conventional MOSFET as a synapse device is needed to support the rapid and unpredictable future changes in the semiconductor industry. Furthermore, research utilizing FDSOI devices includes neuron research, [ 30 ] array neural network, [ 31 ] and neural network research connecting SRAM synapse and SRAM neuron array. [ 32 ] FDSOI MOSFET has advantage of suppressed short channel effect (SCE), low capacitance, low junction leakage, low voltage, and so on.…”

Section: Introductionmentioning

confidence: 99%

“…[32] FDSOI MOSFET has advantage of suppressed short channel effect (SCE), low capacitance, low junction leakage, low voltage, and so on. [30,33] Demonstrating artificial neural networks often requires numerous devices and complex circuits, making low-power devices advantageous. However, there is a dearth of research on the configuration of a hardware-based array system that connects these three hardware-based terminal devices with a neuron device and evaluates the electrical characteristics that regulate pre-and postsynapses accordingly, thus mimicking the human brain.…”

mentioning

confidence: 99%

Synaptic Characteristics of Fully Depleted Silicon‐on‐Insulator Metal‐Oxide‐Semiconductor Field‐Effect Transistors and Synapse‐Neuron Arrayed Neuromorphic Hardware System

Jeon,

Kim,

Akinwande

et al. 2024

Advanced Intelligent Systems

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A fully depleted silicon‐on‐insulator (FDSOI) metal‐oxide‐semiconductor field‐effect transistors (MOSFETs) device is investigated as for an electronic synapse emulating the synaptic functions of the human brain with stable characteristics. Gate‐last processed FDSOI MOSFET with a high‐k/metal gate stack features a memory window of 103. Synaptic conductance is stably regulated by utilizing the FDSOI MOSFET, which offers the advantage of mitigating leakage current when compared to bulk Si MOSFET. Short‐ and long‐term plasticity are investigated by applying engineered pulse, verifying the long‐term synaptic properties of pattern recognition processes. With controllable synaptic conductance, the trade‐off between conductance change and linearity regarding the recognition rate is evaluated, attaining a recognition rate of 0.83. To verify the pre‐ and post‐synaptic weights within a real hardware‐based neuromorphic system, 5 × 6 FDSOI field‐effect transistor (FET) synapse array is interconnected to 10 × 10 leaky integrate‐and‐fire (LIF) neuron array. The synaptic plasticity of FDSOI MOSFET in post‐neurons following neuron firing in the neuron device is successfully demonstrated. These results indicate that FDSOI MOSFET devices could be applicable as synapse devices due to controllability and capability to realize signal transmissions and self‐learning processes simultaneously and used to mimic a synapse neuron network system by configuring a hardware system interconnected with the LIF neuron.

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“…Since the computing unit of such architectures employs thousands of neurons, neuron cells are considered as an effective component from the point of view of saving power consumption and silicon area [7][8][9]. Among all models of neurons, the Leaky Integrate & Fire (LIF) model can be easily implemented by MOS transistors with biological dynamics [10][11]. However, the traditional LIF neurons have a large energy consumption and cannot provide stable spike firing behaviors [12][13][14], which are required to mimic the processing of the cortex [15][16].…”

Section: Introductionmentioning

confidence: 99%

A 300mV Body-biased Silicon Neuron Circuit with High Robustness against Firing Frequency Variation

Quan

2022

Preprint

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This paper presents a body-biased silicon neuron circuit which is capable of operating at ultra-low-voltage supplies and achieves a stable firing frequency. The proposed neuron employs body-biased method to increase charging current into the membrane capacitors for compensating the extra leakage current in the subthreshold region. A second-order low-pass filter, using the property of energy storage in capacitors, is used to reset the membrane potential and implement firing frequency adaption mechanism. Body-biased transistors are as well employed as voltage-controlled resistors to control the current flowing through the membrane capacitance. The circuit is capable of obtaining precise firing frequencies by biasing the body voltages of critical PMOS transistors, which make the circuit usable for frequency coding Spiking Neural Network (SNN). The designed neuron is implemented in 55nm bulk CMOS technology with an area of 400 µm2 that consumes about 639fJ@1kHz. We present circuit post-layout simulation results and demonstrate the circuit’s ability to produce biologically plausible neural dynamics with compact designs, and compare the energy consumption and stability with published state-of-the-art neuron circuits. Finally, the proposed circuit is proved to maintain a good robustness over process variation and Monte Carlo analysis with relative error 2.43% in firing rate of approximate 145Hz.

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Compact and Energy Efficient Neuron With Tunable Spiking Frequency in 22-nm FDSOI

Cited by 7 publications

References 54 publications

Optimization of Leaky Integrate-and-Fire Neuron Circuits Based on Nanoporous Graphene Memristors

Optimization of Leaky Integrate-and-Fire Neuron Circuits Based on Nanoporous Graphene Memristors

Synaptic Characteristics of Fully Depleted Silicon‐on‐Insulator Metal‐Oxide‐Semiconductor Field‐Effect Transistors and Synapse‐Neuron Arrayed Neuromorphic Hardware System

A 300mV Body-biased Silicon Neuron Circuit with High Robustness against Firing Frequency Variation

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