Compact and efficient encryption/decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications

Rouvroy, Gaël; Standaert, François‐Xavier; Quisquater, J.-J.; Legat, Jean-Didier

doi:10.1109/itcc.2004.1286716

Cited by 115 publications

(68 citation statements)

References 3 publications

(3 reference statements)

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“…The design achieved a throughput of 23.57Gbps with 16938 slices of hardware area. G. Rouvroy proposed an efficient solution to combine AES encryption and decryption in one FPGA design keeping focus on low area constraint [10]. The proposed design achieved a throughput of 208Mbps using 163 slices and 3 blocks RAM only.…”

Section: A Fpga Based Cryptosystemmentioning

confidence: 99%

A Low Cost FPGA based Cryptosystem Design for High Throughput Area Ratio

Ibrahim¹,

Ahmed²,

Aslam³

et al. 2017

ijacsa

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Abstract-Over many years, Field Programmable Gated Arrays (FPGA) have been used as a target device for various prototyping and cryptographic algorithm applications. Due to the parallel architecture of FPGAs, the flexibility of cryptographic algorithms can be exploited to achieve high throughputs at the expense of very low chip area. In this research, we propose a low cost FPGA based cryptosystem named as Secure Cipher for high throughput to area ratio. The proposed Secure Cipher is implemented using full loop unroll technique in order to exploit the parallelism of the proposed algorithm. The proposed cryptosystem implementation achieved a throughput of 4600Mbps for encryption. The logic resource utilization of this implementation is 802 logic elements(LE) which yields a throughput to area ratio of 5.735Mbps/LE.

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Section: A Fpga Based Cryptosystemmentioning

confidence: 99%

A Low Cost FPGA based Cryptosystem Design for High Throughput Area Ratio

Ibrahim¹,

Ahmed²,

Aslam³

et al. 2017

ijacsa

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“…There are also serials of implementation schemes [20,21].The best performance implementation of AES-ECB 128-bit on FPGA is Fu's [21]. It uses 17887 slices with 212.5MHz clock frequency, and its highest speed is 27.1Gbps.…”

Section: The Application Of Vlsi In Cryptographymentioning

confidence: 99%

A Direction to Avoid Re-encryption in Cryptographic File Sharing

Chen

Feng

Zeng

2007

Lecture Notes in Computer Science

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Abstract. Almost all cryptographic file sharing systems need re-encryption when the sharing was revoked. These systems differ from each other only in the timing of re-encryption. As re-encryption is an expensive operation, it is significant to avoid re-encryption. The purpose of this paper is to advise a direction to avoid re-encryption and facilitate file sharing in cryptographic file sharing system. A Black-box model is set up to achieve this objective. In the model, FPGA or ASIC chips are used to act as the black-box as they have been extensively researched and applied in cryptography. Some applications of FPGA and ASIC in cryptography are detailed in this paper. Their feasibility to be functioned as the black-box is discussed. Also a software implementation on FPGA is attached with tested and effective performance.

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“…This task is indeed the bottleneck of such a solution. Other image processing blocks, such as decryption [20] or watermarking [21] (see Fig. 2), are far less expensive if we want to reach Digital Cinema throughputs.…”

Section: Proposed Architecturementioning

confidence: 99%

A Flexible Hardware JPEG 2000 Decoder for Digital Cinema

Descampe

Devaux

Rouvroy

et al. 2006

IEEE Trans. Circuits Syst. Video Technol.

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The image compression standard JPEG 2000 proposes a large set of features, useful for today's multimedia applications. Unfortunately, it is much more complex than older standards. Real-time applications, such as Digital Cinema, require a specific, secure and scalable hardware implementation. In this paper, a decoding scheme is proposed with two main characteristics. First, the complete scheme takes place in an FPGA, without accessing any external memory, allowing integration in a secured system. Second, a customizable level of parallelization allows to satisfy a broad range of constraints, depending on the signal resolution. The resulting architecture is therefore ready to meet upcoming Digital Cinema specifications.

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Compact and efficient encryption/decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications

Abstract: Hardware implementations of the Advanced Encryption Standard (AES)Rijndael

Cited by 115 publications

References 3 publications

A Low Cost FPGA based Cryptosystem Design for High Throughput Area Ratio

A Low Cost FPGA based Cryptosystem Design for High Throughput Area Ratio

A Direction to Avoid Re-encryption in Cryptographic File Sharing

A Flexible Hardware JPEG 2000 Decoder for Digital Cinema

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