CommBench-a telecommunications benchmark for network processors

Wolf, Tilman; Franklin, Mark A.

doi:10.1109/ispass.2000.842295

Cited by 149 publications

(86 citation statements)

References 15 publications

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“…In NP fields, three benchmark suites have been previously proposed: CommBench [9], NetBench [5] and NpBench [4]. Wolf et.…”

Section: Network Processor Workloadsmentioning

confidence: 99%

“…al. presented eight selected workloads called CommBench [9] for traditional routers and active routers. CommBench has two groups of benchmarks, namely Header Processing Applications (HPA) and Payload Processing Applications (PPA).…”

Section: Network Processor Workloadsmentioning

confidence: 99%

“…Past studies using CommBench [9] and NetBench [5] contrast network workloads with other benchmarks, such as SPEC [6] and mediabench [7], with respect to instruction set characteristics and memory behaviors. NpBench [4] shows the difference characteristics between control plane and data plane network workloads.…”

Section: Network Processor Workloadsmentioning

confidence: 99%

See 2 more Smart Citations

Exploiting Statically Identified ILP for Network Processor Applications

Lee¹

2010

IJCEE

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Abstract-Along with sharply increasing bandwidth requirements, modern network applications and new protocols demand highly intelligent and sophisticated processing over the network. Since these workloads require processing capability beyond state-of-the-art microprocessors, parallel architectures are required in order to handle the packet data without slowing down line speed. Network processors with various parallel architectures are appearing in the market, however, a thorough investigation of the implications of static versus dynamic scheduling of this class of emerging workloads has not been done. In this paper, we characterize the performance and power dissipation of statically identified ILP architectures, and we also compare them to dynamically scheduled architectures for network processing. In dynamically scheduled architectures, the power consumption of the instruction window greatly increases with increasing issue widths. On the other hand, statically scheduled architectures show better performance, as well as tremendous advantages in power, since they do not have instruction window wakeup/select, reorder buffer, and other scheduling related hardware modules. With the large parallelism and the loop nature of network applications, our experimental analysis supports static scheduling as an appropriate strategy for network processor applications.

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“…In NP fields, three benchmark suites have been previously proposed: CommBench [9], NetBench [5] and NpBench [4]. Wolf et.…”

Section: Network Processor Workloadsmentioning

confidence: 99%

Section: Network Processor Workloadsmentioning

confidence: 99%

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Exploiting Statically Identified ILP for Network Processor Applications

Lee¹

2010

IJCEE

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“…Round Robin fair scheduling algorithm used for bandwidth scheduling on network links, as implemented in switches [28]. DRR is computation intensive.…”

Section: Benchmark II -Commbench Drr Drr Is a Deficitmentioning

confidence: 99%

“…IP packets are split into multiple fragments for which some header fields have to be adjusted and a header checksum computed, before being forwarded [28]. Frag is computation intensive.…”

Section: Benchmark II -Commbench Drr Drr Is a Deficitmentioning

confidence: 99%

Automatic application-specific microarchitecture reconfiguration

Padmanabhan¹,

Cytron²,

Chamberlain³

et al. 2006

Proceedings 20th IEEE International Parallel &Amp; Distributed Processing Symposium

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Speculative Subword Register Allocation in Embedded Processors

Zhang

Gupta

2005

Lecture Notes in Computer Science

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Multimedia and network processing applications make extensive use of subword data. Since registers are capable of holding a full data word, when a subword variable is assigned a register only part of the register is used. We propose an instruction set extension to the ARM embedded processor which allows two data items to reside in a register as long as each of them can be stored in 16 bits. The instructions are used by the register allocator to speculatively move the value of an otherwise spilled variable into a register which has already been assigned to another variable. The move is speculative because it only succeeds if the two values (value already present in the register and the value being moved into the register) can be simultaneously held in the register using 16 bits each. When this value is reloaded for further use, an attempt is first made to retrieve the value from its speculatively assigned register. If this attempt succeeds, load from memory is avoided. On an average our technique avoids 47% of dynamic reloads caused by spills.

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CommBench-a telecommunications benchmark for network processors

Cited by 149 publications

References 15 publications

Exploiting Statically Identified ILP for Network Processor Applications

Exploiting Statically Identified ILP for Network Processor Applications

Automatic application-specific microarchitecture reconfiguration

Speculative Subword Register Allocation in Embedded Processors

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