Combining System Level Modeling with Assertion Based Verification

Dahan, A.; Geist, Daniel; Gluhovsky, L.; Pidan, Dmitry; Shapir, G.; Wolfsthal, Yaron; Benalycherif, L.; Kamidem, R.; Lahbib, Younes

doi:10.1109/isqed.2005.32

Cited by 50 publications

(33 citation statements)

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“…FoCs [35] developed by IBM and MBAC [25][26][27] [57,58,72,79] propose several practical techniques for generating FieldProgrammable Gate Array (FPGA) hardware monitors for Signal Temporal Logic (STL), an extension of MTL handling predicates over the real-values.…”

Section: Lessons Learned and Discussionmentioning

confidence: 99%

First international Competition on Runtime Verification: rules, benchmarks, tools, and final results of CRV 2014

Bartocci

Falcone

Bonakdarpour

et al. 2017

Int J Softw Tools Technol Transfer

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The first international Competition on Runtime Verification (CRV) was held in September 2014, in Toronto, Canada, as a satellite event of the 14th international conference on Runtime Verification (RV'14). The event was organized in three tracks: (1) offline monitoring, (2) online monitoring of C programs, and (3) online monitoring of Java programs. In this paper, we report on the phases and rules, a description of the participating teams and their submitted benchmark, the (full) results, as well as the lessons learned from the competition.

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Section: Lessons Learned and Discussionmentioning

confidence: 99%

First international Competition on Runtime Verification: rules, benchmarks, tools, and final results of CRV 2014

Bartocci

Falcone

Bonakdarpour

et al. 2017

Int J Softw Tools Technol Transfer

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“…The growing popularity of SystemC has motivated research efforts aimed at the verification of SystemC models using assertion-based verification (ABV) -an essential method for validation of hardware and hybrid models [6]. With ABV, the designer asserts properties that capture the design intent in a formal language, e.g., PSL 3 [8] or SVA 4 [20].…”

Section: Introduction Systemcmentioning

confidence: 99%

Monitoring temporal SystemC properties

Tabakov¹,

Vardi²

2010

Eighth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010)

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Abstract-Monitoring temporal SystemC properties is crucial for the validation of functional and transaction-level models, yet the current SystemC standard provides no support for temporal specifications. In this work we describe a temporal monitoring framework for the SystemC specification language defined by Tabakov et al. at FMCAD'08. Our framework uses a very minimal modification of the SystemC kernel, exposing event notifications and simulation phases. The user code is instrumented to allow observation of the relevant parts of the model state. As proof of concept, we use the framework to specify and check properties of two SystemC models. We show that monitoring SystemC properties using this framework has reasonable overhead (0.01% -1%) and has decreasing marginal cost. Finally, we demonstrate that monitoring at different levels of abstraction requires very small changes to the specification and the generated monitors. Based on our empirical results we argue that the additional expressive powers and flexibility of the framework does not incur a serious performance hit.

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“…[7,8,9,10,11]). The two most prominent tools for the synthesis of monitor circuits from the simple subset of PSL are FoCs [12], developed at IBM Haifa, and MBAC by Boulé and Zilic [13]. For unrestricted temporal logic, an automata-theoretic construction (based on determinization) is due to Armoni et al [14].…”

Section: Introductionmentioning

confidence: 99%

Monitor Circuits for LTL with Bounded and Unbounded Future

Finkbeiner

Kuhtz

2009

Runtime Verification

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Abstract. Synthesizing monitor circuits for LTL formulas is expensive, because the number of flip-flops in the circuit is exponential in the length of the formula. As a result, the IEEE standard PSL recommends to restrict monitoring to the simple subset and use the full logic only for static verification. We present a novel construction for the synthesis of monitor circuits from specifications in LTL. In our construction, only subformulas with unbounded-future operators contribute to the exponential blowup. We split the specification into a bounded and an unbounded part, apply specialized constructions for each part, and then compose the results into a monitor for the original specification. Since the unbounded part in practical specifications is often very small, we argue that, with the new construction, it is no longer necessary to restrict runtime verification to the simple subset.

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Combining System Level Modeling with Assertion Based Verification

Cited by 50 publications

References 1 publication

First international Competition on Runtime Verification: rules, benchmarks, tools, and final results of CRV 2014

First international Competition on Runtime Verification: rules, benchmarks, tools, and final results of CRV 2014

Monitoring temporal SystemC properties

Monitor Circuits for LTL with Bounded and Unbounded Future

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