Combining structural and timing errors in overclocked inexact speculative adders

Abstract

Abstract-Worst-case design is used in IoT devices and high performance data centers to ensure reliability, leading to a power efficiency loss. Recently, approximate computing has been proposed to trade off accuracy for efficiency. In this paper, we use Inexact Speculative Adders, which redesign the adder architecture to shorten its critical path and improve performance, but introduces controlled structural errors. On the other hand, overclocking is used to reduce conservative timing guardbands but could normally introduce catastrophic timing errors, we thus apply a supervised learning model to overclock speculative adders and predict their timing errors. We build a methodology to combine both structural and timing errors and analyze how they interplay with each other to limit the overal errors.

Approximate FPGA Implementation of CORDIC for Tactile Data Processing Using Speculative Adders

“…This technique allows to precisely control mean and maximum errors. It has also shown significant benefits compared or combined with other low-power techniques [25]- [27] or successfully integrated within bigger ASIC systems [28]. In the case of FPGA, the ISA could be particularly interesting in order to overcome FPGA's hardware limitations, e.g.…”