Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver

Ganai, Malay K.; Ashar, Pranav; Gupta, Aarti; Zhang, Lintao; Malik, Sharad

doi:10.1145/514100.514105

Cited by 30 publications

(47 citation statements)

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“…More recently there has been an effort by Ganai et al [41] to combine the relative benefits of CNF-based and circuit-based SAT solvers. In particular, their hybrid SAT solver incorporates efficient circuit-based BCP techniques, along with conflict analysis techniques of CNFbased solvers.…”

Section: Hybrid Sat Solversmentioning

confidence: 99%

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A survey of recent advances in SAT-based formal verification

Prasad

Biere

Gupta³

2005

Int J Softw Tools Technol Transfer

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202

120

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Abstract. Dramatic improvements in SAT solver technology over the last decade and the growing need for more efficient and scalable verification solutions have fueled research in verification methods based on SAT solvers. This paper presents a survey of the latest developments in SAT-based formal verification, including incomplete methods such as bounded model checking and complete methods for model checking. We focus on how the surveyed techniques formulate the verification problem as a SAT problem and how they exploit crucial aspects of a SAT solver, such as application-specific heuristics and conflict-driven learning. Finally, we summarize the noteworthy achievements in this area so far and note the major challenges in making this technology more pervasive in industrial design verification flows.

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Section: Hybrid Sat Solversmentioning

confidence: 99%

“…A slight tuning of these heuristics for the BMC problem [88] can fur-ther enhance the performance. On the other hand, BMC tools using circuit-based SAT solvers (e.g., [41,59,64]) essentially use some variant of the J-frontier justification heuristic popularly used in sequential ATPG tools.…”

Section: Decision Variable Ordering Of the Sat Solvermentioning

confidence: 99%

A survey of recent advances in SAT-based formal verification

Prasad

Biere

Gupta³

2005

Int J Softw Tools Technol Transfer

Self Cite

202

120

View full text Add to dashboard Cite

show abstract

“…Given a design and a correctness property, it generates a Boolean formula, such that the formula is true if and only if there exists a witness/counterexample of length k. This formula is then checked by a backend SAT solver. Due to the many recent advances in SAT solvers [9][10][11][12][13], SAT-based BMC can handle much larger designs and analyze them faster than before.…”

Section: Introductionmentioning

confidence: 99%

“…The problem is known to be NP-complete. Most SAT solvers [9][10][11][12][13] employ DPLL style [24] algorithm as shown in Figure 2 with three main engines: decision, deduction, and diagnosis. A Boolean problem can be expressed either in CNF form or logical gate form or both.…”

Section: Introductionmentioning

confidence: 99%

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Efficient Distributed SAT and SAT-Based Distributed Bounded Model Checking

Ganai¹,

Gupta²,

Yang³

et al. 2003

Lecture Notes in Computer Science

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Abstract. SAT-based Bounded Model Checking (BMC), though a robust and scalable verification approach, still is computationally intensive, requiring large memory and time. Interestingly, with the recent development of improved SAT solvers, it is frequently the memory limitation of a single server rather than time that becomes a bottleneck for doing deeper BMC search. Distributing computing requirements of BMC over a network of workstations can overcome the memory limitation of a single server, albeit at increased communication cost. In this paper, we present: a) a method for distributed-SAT over a network of workstations using a Master/Client model where each Client worsktation has an exclusive partition of the SAT problem and uses knowledge of partition topology to communicate with other Clients, b) a method for distributing SATbased BMC using the distributed-SAT. For the sake of scalability, at no point in the BMC computation does a single workstation have all the information. We experimented on a network of heterogenous workstations interconnected with a standard Ethernet LAN. To illustrate, on an industrial design with ~13K FFs and ~0.5M gates, the non-disributed BMC on a single workstation (with 4 Gb memory) ran out of memroy after reaching a depth of 120; on the otherhand, our SAT-based distributed BMC over 5 similar workstations was able to go upto 323 steps with a communication overhead of only 30%.

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CirCUs: A Hybrid Satisfiability Solver

Jin¹,

Somenzi²

2005

Theory and Applications of Satisfiability Testing

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CirCUs is a satisfiability solver that works on a combination of an And-Inverter-Graph (AIG), Conjunctive Normal Form (CNF) clauses, and Binary Decision Diagrams (BDDs). We show how BDDs are used by CirCUs to help in the solution of SAT instances given in CNF. Specifically, the clauses are sorted by solving a hypergraph linear arrangement problem. Then they are clustered by an algorithm that strives to avoid explosion in the resulting BDD sizes. If clustering results in a single diagram, the SAT instance is solved directly. Otherwise, search for a satisfying assignment is conducted on the original clauses, enhanced with information extracted from the BDDs. We also describe a new decision variable selection heuristic that is based on recognizing that the variables involved in a conflict clause are often best treated as a related group. We present experimental results that demonstrate Cir-CUs's efficiency especially for medium-size SAT instances that are hard to solve by traditional solvers based on DPLL.

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Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver

Cited by 30 publications

References 0 publications

A survey of recent advances in SAT-based formal verification

A survey of recent advances in SAT-based formal verification

Efficient Distributed SAT and SAT-Based Distributed Bounded Model Checking

CirCUs: A Hybrid Satisfiability Solver

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