Combining PREM compilation and static scheduling for high-performance and predictable MPSoC execution

Abstract

Many applications require both high performance and predictable timing. High-performance can be provided by COTS Multi-Core System on Chips (MPSoC), however, as cores in these systems share main memory, they are susceptible to interference from each other, which is a problem for timing predictability. We achieve predictability on multi-cores by employing the predictable execution model (PREM), which splits execution into a sequence of memory and compute phases, and schedules these such that only a single core is executing a memory phase at a time.We present a toolchain consisting of a compiler and a scheduling tool. Our compiler uses region and loop based analysis and performs tiling to transform application code into PREM-compliant binaries. In addition to enabling predictable execution, the compiler transformation optimizes accesses to the shared main memory.The scheduling tool uses a state-of-the-art heuristic algorithm and is able to schedule industrial-size instances. For smaller instances, we compare the results of the algorithm with optimal solutions found by solving an Integer Linear Programming model. Furthermore, we solve the problem of scheduling execution on multiple cores while preventing interference of memory phases.We evaluate our toolchain on Advanced Driver Assistance System (ADAS) application workloads running on an NVIDIA Tegra X1 embedded system-on-chip (SoC). The results show that our approach maintains similar average performance to the original (unmodified) program code and execution, while reducing variance of completion times by a factor of 9 with the identified optimal solutions and by a factor of 5 with schedules generated by our heuristic scheduler.

A Synergistic Approach to Predictable Compilation and Scheduling on Commodity Multi-Cores

“…Due to the complexity of making programs PREM-compliant, compiler support has been proposed [9,14] to automatically identify code segments that fulfil the requirements of Equation 1, and transform these segments into PREM intervals of prefetch, compute, and writeback phases. The following section outlines three of the major components of PREM compilers [9,14] that impact the final PREM system.…”

“…All recently proposed PREM compilers [4,9,14] use Single Entry Single Exit (SESE) regions as the atomic unit from which PREM intervals are created. SESE regions are code regions represented by every part of the Control Flow Graph (CFG) that only has a single incoming edge and a single outgoing edge.…”

“…For the compiler to create intervals that respect the requirement of Equation 1, the memory footprint (i.e., size in bytes of data accessed) of all regions must be calculated. This can be calculated as outlined in [9,14]. For the remainder of the discussion we assume this methodology is used.…”

“…As outlined previously, there are two fundamental types of regions: sequential regions and loops [9].…”

“…Memory interference is avoided by finding a system schedule that maps each interval i to a core c, and globally scheduling the system such that only a single core c is executing the memory phase of an interval i at a time. Scheduling techniques to achieve this are readily available in the literature [1,9,18], and as all share the fundamental requirement that only one task is executing its memory phase at once, the total response time R τ of a task τ can be generically modeled as shown in Equation 2.…”