Combining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systems

Abstract

It is well-known that memory latency, energy, capacity, bandwidth, and scalability will be critical bottlenecks in future large-scale systems. This paper addresses these problems, focusing on the interface between the compute cores and memory, comprising the physical interconnect and the memory access protocol. For the physical interconnect, we study the prudent use of emerging silicon-photonic technology to reduce energy consumption and improve capacity scaling. We conclude that photonics are effective primarily to improve socket-edge bandwidth by breaking the pin barrier, and for use on heavily utilized links. For the access protocol, we propose a novel packet based interface that relinquishes most of the tight control that the memory controller holds in current systems and allows the memory modules to be more autonomous, improving flexibility and interoperability. The key enabler here is the introduction of a 3D-stacked interface die that allows both these optimizations without modifying commodity memory dies. The interface die handles all conversion between optics and electronics, as well as all low-level memory device control functionality. Communication beyond the interface die is fully electrical, with TSVs between dies and low-swing wires on-die. We show that such an approach results in substantially lowered energy consumption, reduced latency, better scalability to large capacities, and better support for heterogeneity and interoperability.

Designing Chip-Level Nanophotonic Interconnection Networks

“…More complicated physical design (e.g., redundant transmitters and optical power guiding) may have some implications on the electrical control logic and thus the network's microarchitecture, but it is important to note that these techniques are solely focused on mitigating physical design issues and do not fundamentally change the logical network topology. Most nanophotonic buses in the literature use wavelength slicing [1], [2], [4] and there has been some work on the impact of split nanophotonic buses [4], and guided nanophotonic buses [3].…”

“…Fig. 9(b) illustrates a double-serpentine layout for a 4 4 SWMR crossbar with one wavelength per bus and a single waveguide. In this layout, waveguides are "snaked" by each terminal twice with light traveling in one direction.…”

“…1, the silicon ring resonator is used in transmitters, passive filters, and receivers. Although other photonic structures (e.g., Mach-Zehnder interferometers) are possible, ring modulators are extremely compact (3)(4)(5)(6)(7)(8)(9)(10) radius) resulting in reduced area and power consumption. Although not shown in Fig.…”

Indium-Tin-Oxide for High-performance Electro-optic Modulation

“…The advantage of such sub-diffraction limited photonics is two-fold; reduced optical power requirements and physical device size. To elaborate on this, while being physically compact, the optical mode confinement of such components can strongly enhance light matter interactions (LMI) [5,6], which can reduce required drive power to obtain the desired effect, for example, signal modulation, optical non-linearities [7,8]. In order to address these demands, photonic components and even circuits based on surface plasmon polaritons (SPPs), collective oscillations of electrons at metal-dielectric interfaces are thought of a solution for nanoscale PICs [9].…”

“…To this end, a low-loss platform would build the backend data link, for example, silicon-on-insulator (SOI) based waveguides [12], while SPP-based components offer compact and efficient light manipulation [5,6,[13][14][15][16]. Therefore, these components are required to fulfil two design criteria; strong mode confinement and a sufficiently long propagation length to utilize the mode towards light manipulating effect or signal [17,18].…”