The polarity-dependent resistive-switching across metal-Pr0.7Ca0.3MnO3 interfaces is investigated. The data suggest that shallow defects in the interface dominate the switching. Their density and fluctuation, therefore, will ultimately limit the device size. While the defects generated/annihilated by the pulses and the associated carrier depletion seem to play the major role at lower defect density, the defect correlations and their associated hopping ranges appear to dominate at higher defect density. Therefore, the switching characteristics, especially the size-scalability, may be altered through interface treatments.The renewed interest in various resistive switching phenomena is largely driven by recent market demands for nano-sized nonvolatile memory devices. 1 While the current boom of consumer electronics may largely be attributed to the successful miniaturization of both FLASH chips and mini hard drives, cheaper and smaller devices are called for.Various resistive hysteretic phenomena are consequently studied with the hope that the size limitations associated with the related physics/chemistry/technology might be less severe. 2 Our limited knowledge about the mechanisms so far, however, makes the evaluation difficult. This is especially true for the switching across metal-Pr 0.7 Ca 0.3 MnO 3 (PCMO) interfaces. 3,4,5,6 Several models, i.e. bulk phase-separation, 3 carrier-trapping in pre-existing metallic domains, 7,8 and field-induced lattice defects, 4 have been proposed. Each possesses its own distinguishable size-limitation, e.g. the statistics of the associated local mesostructures. Here, we report our mechanism investigation through both the trapped-carrier distribution and their hopping range. Our data suggest that the characteristics may largely be engineered through the mesostructure of the interfacial defects.Bulk PCMO, in great contrast with well known semiconductors, has a rather high nominal carrier concentration with its high resistivity mainly attributed to hopping barriers. 9 Local defects, therefore, appear as a natural cause of the resistive switching. Following this line of reasoning, a domain model has recently attracted much attention. 7,8 There, a tunneling from the electrode to some pre-existing interfacial metallic domains has been assumed to be the dominant process. Consequently, the carrier-occupation in the domains may change with the carrier-trapping during the write pulses, and cause the Rswitch between an on (low resistance) and an off (high resistance) state. This is realized through either the change of the tunneling probability 7 or a doping-induced metalinsulator transition. 8 Useful devices based on this mechanism, therefore, should typically be much larger than these interfacial domains. It is interesting to note that even if the "domains" can be reduced to individual lattice defects (or small clusters) as in the proposed defect modification model, 4 the fluctuation (inhomogeneity) of the defect density still sets a limit for the size scalability just like the dopant fl...