Collection of Charge on Junction Nodes from Ion Tracks

Messenger, George C.

doi:10.1109/tns.1982.4336490

Cited by 581 publications

(192 citation statements)

References 6 publications

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“…When t=10 ns, a low state is written to Q and a high state is written to Qb and when t=12 ns, the single-event hit is simulated. The current pulse that results from a particle strike is traditionally described as a double exponential function [1] as follows:…”

Section: Simulation Results and Evaluationmentioning

confidence: 99%

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A novel single event upset hardened CMOS SRAM cell

Zhang

Shao

Liang

et al. 2012

IEICE Electron. Express

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This paper presents an improved design of a radiationhardened static random access memory (SRAM). The simulation results based on the 0.18 μm standard digital CMOS technology show that its static current drops dramatically compared with the WHIT cell, and the write speed is equivalent to that of other cells. The memory cell is extremely tolerant to logic upset as it does not flip even for a transient pulse with 100 times the critical charge of the ROCK cell. According to these features, this novel cell suits high reliability applications, such as aerospace and military.

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Section: Simulation Results and Evaluationmentioning

confidence: 99%

“…Semiconductor memories occupy large area in modern integrated circuits. A high energy charged particle may change the content of a memory cell when energetic particles (ions) strike the storage cell's sensitive node [1,2]. Preventing such a single event upset (SEU) will be a great challenge to the designers of reliable space based systems.…”

Section: Introductionmentioning

confidence: 99%

A novel single event upset hardened CMOS SRAM cell

Zhang

Shao

Liang

et al. 2012

IEICE Electron. Express

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“…These results are used in our experiments in Section 4. In addition, from the statistical energy distribution we are able to model the statistical SET widths in logic circuit by applying the LET values to the commonly used transient current double-exponential model [7].…”

Section: An Environment-based Probabilistic Soft Error Modelmentioning

confidence: 99%

Soft Error Rate Determination for Nanometer CMOS VLSI Logic

Wang

Agrawal

2008

2008 40th Southeastern Symposium on System Theory (SSST)

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“…Device feature sizes were 7 _pm, or larger, and many of the "exotic" technologies showing promise today, including trenched DRAM technologies and insulated technologies, were not even a gleam in designers' eyes. Charge collection by IC devices from ion tracks had not been accurately described analytically; field funneling [62,79,80] had not been "discovered". Still, single-event upset had been predicted as a "fundamental limit" on IC scaling [81], and single-event upsets had been "discovered" in space-borne ICs [82].…”

Section: Introductionmentioning

confidence: 99%