Coherency Hub Design for Multisocket Sun Servers with CoolThreads Technology

Feehrer, John; Rotker, P.; Shih, M.; Gingras, P.; Yakutis, Peter; Phillips, Stephen; Heath, John R.

doi:10.1109/mm.2009.62

Cited by 4 publications

(3 citation statements)

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“…With only tens of threads per core, CPU coherence implementations can dedicate enough on-chip storage resources to buffer the worst case number of coherence requests [18]. GPUs, however, execute tens of thousands of scalar threads in parallel.…”

Section: Storage Requirementsmentioning

confidence: 99%

“…GPUs, however, execute tens of thousands of scalar threads in parallel. In a CPU-like coherence implementation [18] with enough storage to handle the worst case number of memory accesses (one memory request per thread), a directory protocol would require an impractical on-chip buffer as large as 28% of the total GPU L2 cache for tracking coherence requests. Reducing the worstcase storage overhead requires throttling the network via back-pressure flow-control mechanisms when the end-point queues fill up [37].…”

Section: Storage Requirementsmentioning

confidence: 99%

“…Second, on a GPU, CPU-like worst case sizing [18] would require an impractical amount of storage for tracking thousands of in-flight coherence requests. Third, existing coherence protocols introduce complexity in the form of transient states and additional message classes.…”

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confidence: 99%

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Cache Coherence for GPU Architectures

et al. 2014

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While scalable coherence has been extensively studied in the context of general purpose chip multiprocessors (CMPs), GPU architectures present a new set of challenges.Introducing conventional directory protocols adds unnecessary coherence traffic overhead to existing GPU applications. Moreover, these protocols increase the verification complexity of the GPU memory system. Recent research, Library Cache Coherence (LCC) [34,54], explored the use of time-based approaches in CMP coherence protocols.This paper describes a time-based coherence framework for GPUs, called Temporal Coherence (TC), that exploits globally synchronized counters in single-chip systems to develop a streamlined GPU coherence protocol. Synchronized counters enable all coherence transitions, such as invalidation of cache blocks, to happen synchronously, eliminating all coherence traffic and protocol races. We present an implementation of TC, called TC-Weak, which eliminates LCC's trade-off between stalling stores and increasing L1 miss rates to improve performance and reduce interconnect traffic.By providing coherent L1 caches, TC-Weak improves the performance of GPU applications with inter-workgroup communication by 85% over disabling the non-coherent L1 caches in the baseline GPU. We also find that write-through protocols outperform a writeback protocol on a GPU as the latter suffers from increased traffic due to unnecessary refills of write-once data. IntroductionGraphics processor units (GPUs) have become ubiquitous in high-throughput, general purpose computing. C-based programming interfaces like OpenCL [29] and NVIDIA CUDA [46] ease GPU programming by abstracting away the SIMD hardware and providing the illusion of independent scalar threads executing in parallel. Tra-0.5

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Section: Storage Requirementsmentioning

confidence: 99%

Section: Storage Requirementsmentioning

confidence: 99%

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Cache Coherence for GPU Architectures

et al. 2014

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Cache coherence for GPU architectures

Singh¹,

Shriraman

Fung³

et al. 2013

2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)

123

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While scalable coherence has been extensively studied in the context of general purpose chip multiprocessors (CMPs), GPU architectures present a new set of challenges. Introducing conventional directory protocols adds unnecessary coherence traffic overhead to existing GPU applications. Moreover, these protocols increase the verification complexity of the GPU memory system. Recent research, Library Cache Coherence (LCC) [34,54], explored the use of time-based approaches in CMP coherence protocols.This paper describes a time-based coherence framework for GPUs, called Temporal Coherence (TC), that exploits globally synchronized counters in single-chip systems to develop a streamlined GPU coherence protocol. Synchronized counters enable all coherence transitions, such as invalidation of cache blocks, to happen synchronously, eliminating all coherence traffic and protocol races. We present an implementation of TC, called TC-Weak, which eliminates LCC's trade-off between stalling stores and increasing L1 miss rates to improve performance and reduce interconnect traffic.By providing coherent L1 caches, TC-Weak improves the performance of GPU applications with inter-workgroup communication by 85% over disabling the non-coherent L1 caches in the baseline GPU. We also find that write-through protocols outperform a writeback protocol on a GPU as the latter suffers from increased traffic due to unnecessary refills of write-once data.

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