Cognitive computing systems: Algorithms and applications for networks of neurosynaptic cores

Esser, Steven K.; Andreopoulos, Alexander; Appuswamy, Raja; Datta, Pallab; Davis, Kei; Amir, Arnon; Arthur, John V.; Cassidy, Andrew; Flickner, Myron; Merolla, Paul; Chandra, Shyamal; Basilico, Nicola; Carpin, Stefano; Zimmerman, T.; Zee, F.; Alvarez-Icaza, Rodrigo; Kusnitz, Jeffrey A.; Wong, Theodore M.; Risk, W. P.; McQuinn, Emmett; Nayak, T. K.; Singh, R. V.; Modha, Dharmendra S.

doi:10.1109/ijcnn.2013.6706746

Cited by 96 publications

(54 citation statements)

References 20 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In this platform the synapses do not implement any plasticity mechanism, therefore they are not able to perform on-line learning. TrueNorth is used to recognize and classify MNIST dataset images using unsupervised learning in RBM architecture [29]. The system scored 91.94 % using 60,000 samples for training set and 10,000 samples of test set.…”

Section: Hardware Spiking Neural Network Sys-tem Surveymentioning

confidence: 99%

Parameter Exploration to Improve Performance of Memristor-Based Neuromorphic Architectures

Shahsavari

Boulet

2018

IEEE Trans. Multi-Scale Comp. Syst.

View full text Add to dashboard Cite

Abstract-The brain-inspired spiking neural network neuromorphic architecture offers a promising solution for a wide set of cognitive computation tasks at a very low power consumption. Due to the practical feasibility of hardware implementation, we present a memristor-based model of hardware spiking neural networks which we simulate with N2S3 (Neural Network Scalable Spiking Simulator), our open source neuromorphic architecture simulator. Although Spiking neural networks are widely used in the community of computational neuroscience and neuromorphic computation, there is still a need for research on the methods to choose the optimum parameters for better recognition efficiency. With the help of our simulator, we analyze and evaluate the impact of different parameters such as number of neurons, STDP window, neuron threshold, distribution of input spikes and memristor model parameters on the MNIST hand-written digit recognition problem. We show that a careful choice of a few parameters (number of neurons, kind of synapse, STDP window and neuron threshold) can significantly improve the recognition rate on this benchmark (around 15 points of improvement for the number of neurons, a few points for the others) with a variability of 4 to 5 points of recognition rate due to the random initialization of the synaptic weights.

show abstract

Section: Hardware Spiking Neural Network Sys-tem Surveymentioning

confidence: 99%

Parameter Exploration to Improve Performance of Memristor-Based Neuromorphic Architectures

Shahsavari

Boulet

2018

IEEE Trans. Multi-Scale Comp. Syst.

View full text Add to dashboard Cite

show abstract

“…IBM â 's CoreLet â (Amir, 2013) language is closely bound to the TrueNorth â (Cassidy, 2013) neural processing chips, where simple spiking neuron circuits are interconnected in cross-bar fashion and such assemblies are linked together to perform cognitive functions (Esser, 2013). The Neural Engineering Framework (Stewart, 2012) offers component creation based on parameterized distributed neural networks of spiking neurons.…”

Section: Related Workmentioning

confidence: 99%

NeurOS™ and NeuroBlocks™ a neural/cognitive operating system and building blocks

Scheffler

2015

Biologically Inspired Cognitive Architectures

View full text Add to dashboard Cite

NeurOS is an open platform for accelerating research, development and hosting execution of intelligent applications. A NeurOS application is a directed ''neural graph'' of modular components connected by signal paths, similar to biological brain connectivity and functional block diagrams of neural pathways. Built-in reusable modules (NeuroBlocks) provide a wide range of general-and special-purpose capabilities: inputs/senses, outputs/effectors, processing, memory, pattern learning and recognition, visualization/instrumentation, custom module development, integrating external intelligence capabilities, and sub-graph reuse. NeurOS sub-graph assemblies address neural/cognitive functions including perception, pattern learning and recognition, working memory, imagination, prediction, context priming, attention, abstraction, classification, associational thinking and behavior. NeurOS applications are inherently portable, scalable, networkable, extensible and embeddable. NeurOS development tools provide simple intuitive graphical drag and drop application assembly from components without programming, along with testing, debugging, monitoring and visualization. Prototype NeurOS applications have begun to explore a wide range of intelligent functions in diverse areas, including aspects of pattern recognition, vision, music, reading, puzzle solving, reasoning, behavior. Building working intelligent systems using NeurOS and NeuroBlocks lets researchers and developers focus on their core functions and rapidly iterate and instrument working models, fostering both analytical and biological insight as well as usable systems.

show abstract

“…Our optimized simulator, Compass, is functionally 1:1 equivalent with TrueNorth via codesign [16], [17]. As a result, we have developed a cache of applications on Compass [18], such as multi-sensory feature extraction and pattern recognition; association and context processing; as well as information extraction, that now run without modification on TrueNorth, orders of magnitude faster and for orders of magnitude less energy.…”

Section: Overviewmentioning

confidence: 99%

“…We have implemented two expressions of the blueprint, co-designing a scalable supercomputerbased simulator (Compass [6]) and a scalable silicon-fabricated processor (TrueNorth [12]), ensuring identical one-to-one operation, such that any model on the software simulator runs unchanged on the hardware. Enablements or infrastructure includes an architecture specific "Corelet" language and Corelet Programming Environment (CPE) [19], a library of algorithms [18] in CPE, and Compass to simulate networks and to facilitate training off-line. We developed Applications that ran initially on Compass-even before TrueNorth was fabricated and tested-and later (without modification) on TrueNorth, including convolutional networks, liquid state machines, restricted Boltzmann machines, hidden Markov models, support vector machines, and optical flow [18].…”

Section: Related Workmentioning

confidence: 99%

“…Enablements or infrastructure includes an architecture specific "Corelet" language and Corelet Programming Environment (CPE) [19], a library of algorithms [18] in CPE, and Compass to simulate networks and to facilitate training off-line. We developed Applications that ran initially on Compass-even before TrueNorth was fabricated and tested-and later (without modification) on TrueNorth, including convolutional networks, liquid state machines, restricted Boltzmann machines, hidden Markov models, support vector machines, and optical flow [18]. To promulgate the new ecosystem, we have developed a new teaching curriculum.…”

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Real-Time Scalable Cortical Computing at 46 Giga-Synaptic OPS/Watt with ~100× Speedup in Time-to-Solution and ~100,000× Reduction in Energy-to-Solution

Cassidy

Alvarez-Icaza

Akopyan

et al. 2014

SC14: International Conference for High Performance Computing, Networking, Storage and Analysis

Self Cite

View full text Add to dashboard Cite

Drawing on neuroscience, we have developed a parallel, event-driven kernel for neurosynaptic computation, that is efficient with respect to computation, memory, and communication. Building on the previously demonstrated highlyoptimized software expression of the kernel, here, we demonstrate TrueNorth, a co-designed silicon expression of the kernel. TrueNorth achieves five orders of magnitude reduction in energyto-solution and two orders of magnitude speedup in time-tosolution, when running computer vision applications and complex recurrent neural network simulations. Breaking path with the von Neumann architecture, TrueNorth is a 4,096 core, 1 million neuron, and 256 million synapse brain-inspired neurosynaptic processor, that consumes 65mW of power running at real-time and delivers performance of 46 Giga-Synaptic OPS/Watt. We demonstrate seamless tiling of TrueNorth chips into arrays, forming a foundation for cortex-like scalability. TrueNorth's unprecedented time-to-solution, energy-to-solution, size, scalability, and performance combined with the underlying flexibility of the kernel enable a broad range of cognitive applications.

show abstract

Cognitive computing systems: Algorithms and applications for networks of neurosynaptic cores

Cited by 96 publications

References 20 publications

Parameter Exploration to Improve Performance of Memristor-Based Neuromorphic Architectures

Parameter Exploration to Improve Performance of Memristor-Based Neuromorphic Architectures

NeurOS™ and NeuroBlocks™ a neural/cognitive operating system and building blocks

Real-Time Scalable Cortical Computing at 46 Giga-Synaptic OPS/Watt with ~100× Speedup in Time-to-Solution and ~100,000× Reduction in Energy-to-Solution

Contact Info

Product

Resources

About

Cognitive computing systems: Algorithms and applications for networks of neurosynaptic cores

Cited by 96 publications

References 20 publications

Parameter Exploration to Improve Performance of Memristor-Based Neuromorphic Architectures

Parameter Exploration to Improve Performance of Memristor-Based Neuromorphic Architectures

NeurOS™ and NeuroBlocks™ a neural/cognitive operating system and building blocks

Real-Time Scalable Cortical Computing at 46 Giga-Synaptic OPS/Watt with ~100&#x00D7; Speedup in Time-to-Solution and ~100,000&#x00D7; Reduction in Energy-to-Solution

Contact Info

Product

Resources

About

Real-Time Scalable Cortical Computing at 46 Giga-Synaptic OPS/Watt with ~100× Speedup in Time-to-Solution and ~100,000× Reduction in Energy-to-Solution