Code-density calibration of Nyquist-rate analog-to-digital converters

Abstract

An analog-to-digital converter (ADC) calibration algorithm based on measuring and correcting the code-density histogram of the converter under calibration is presented. The algorithm constructs a histogram of the ADC response to a linear ramp and stores the calculated correction coefficients in a lookuptable. By leveraging circuit density improvements in deep submicron CMOS technology, the algorithm is able to provide substantive improvements to ADC static linearity performance at low silicon cost. The algorithm is applied to a 12-stage prototype Pipelined ADC implemented in 65 nm CMOS technology and is able to improve measured integral nonlinearity from -5.31/1.02 least significant bit (LSB) to -0.24/0.31 LSB at a 10-bit level, an improvement of over three effective bits.

A 7.4-Bit ENOB 600 MS/s FPGA-Based Online Calibrated Slope ADC without External Components

“…Different from the average calibration method, the delay time of each delay cell can be calculated through the code density test. The principle of the code density test in TDC is similar to that in ADC [ 31 ]. The difference is that the code density test in ADC is the quantitative statistical analysis of voltage with random amplitude, while the code density test in TDC is the quantitative statistics with completely random time intervals.…”