Code Compression and Decompression for Coarse-Grain Reconfigurable Architectures

Aslam, N.; Milward, M.; Erdogan, A.T.; Arslan, Tughrul

doi:10.1109/tvlsi.2008.2001562

Cited by 11 publications

(14 citation statements)

References 10 publications

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“…Table 7 shows the compression ratio comparison with both post-context-generation methods. As can be seen, the proposed method outperforms both dictionary-based compression [8] and dynamic compression [7]. Considering both of them need extra hardware support, the proposed method has more obvious advantages.…”

Section: Comparison With Post-context-generation Methodsmentioning

confidence: 89%

“…We also compare our proposed method with two postcontext-generation methods, DCC [7] and CS3 [8], in terms of the context compression ratio and execution performance. Table 6 shows the comparison results for context size and compression ratio.…”

Section: Comparison With Post-context-generation Methodsmentioning

confidence: 99%

“…This power-efficient design of context architecture works without degrading the performance and flexibility of coarse-grained reconfigurable architecture. In [8], a dictionary-based lossless context compression scheme and its corresponding decompressor hardware unit are proposed. All above methods have a common feature that they compress context based on statistical characteristics of configuration bitstream just like traditional data compression.…”

Section: Introductionmentioning

confidence: 99%

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Configuration Context Reduction for Coarse-Grained Reconfigurable Architecture

Yin

Liu

et al. 2012

IEICE Trans. Inf. & Syst.

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SUMMARYCoarse-grained reconfigurable architecture (CGRA) combines the performance of application-specific integrated circuits (ASICs) and the flexibility of general-purpose processors (GPPs), which is a promising solution for embedded systems. With the increasing complexity of reconfigurable resources (processing elements, routing cells, I/O blocks, etc.), the reconfiguration cost is becoming the performance bottleneck. The major reconfiguration cost comes from the frequent memory-read/write operations for transferring the configuration context from main memory to context buffer. To improve the overall performance, it is critical to reduce the amount of configuration context. In this paper, we propose a configuration context reduction method for CGRA. The proposed method exploits the structure correlation of computation tasks that are mapped onto CGRA and reduce the redundancies in configuration context. Experimental results show that the proposed method can averagely reduce the configuration context size up to 71% and speed up the execution up to 68%. The proposed method does not depend on any architectural feature and can be applied to CGRA with an arbitrary architecture.

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Section: Comparison With Post-context-generation Methodsmentioning

confidence: 89%

Section: Comparison With Post-context-generation Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Configuration Context Reduction for Coarse-Grained Reconfigurable Architecture

Yin

Liu

et al. 2012

IEICE Trans. Inf. & Syst.

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“…The first interesting finding discovered through our observation is that many frequently executed code on a specific FU are also frequently executed on other FUs in a CGRA. It means that per-FU dictionaries (local dictionaries), which is an idea in [3],have duplicated codes.We reduced this inefficiency using a global dictionary, a common dictionary for all FUs saving most frequently executed code across the FUs.…”

Section: B Instruction Analysis and Lessonsmentioning

confidence: 99%

“…However, as shown in the fifth column in the TABLE I, the advanced compiler does not generate as many NOPs. The sixth and seventh columns show that the Location Tag bit width and average overhead for each group when the work in [3] is applied to the target code of this paper. The Location Tag is a prefix for all compressed code that indicates its target composition.…”

Section: B Nop Eliminationmentioning

confidence: 99%

Adaptive compression for instruction code of Coarse Grained Reconfigurable Architectures

Chung

Kim

Cho

et al. 2013

2013 International Conference on Field-Programmable Technology (FPT)

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Coarse Grained Reconfigurable Architecture (CGRA) achieves high performance by exploiting instructionlevel parallelism with software pipeline. Large instruction memory is, however, a critical problem of CGRA, which requires large silicon area and power consumption. Code compression is a promising technique to reduce the memory area, bandwidth requirements, and power consumption. We present an adaptive code compression scheme for CGRA instructions based on dictionary-based compression, where compression mode and dictionary contents are adaptively selected for each execution kernel and compression group. In addition, it is able to design hardware decompressor efficiently with two-cycle latency and negligible silicon overhead. The proposed method achieved an average compression ratio 0.52 in a CGRA of 16-functional unit array with the experiments of well-optimized applications.

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Architecture, challenges and applications of dynamic reconfigurable computing

Liu

Zhu

et al. 2020

J. Semicond.

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As a computing paradigm that combines temporal and spatial computations, dynamic reconfigurable computing provides superiorities of flexibility, energy efficiency and area efficiency, attracting interest from both academia and industry. However, dynamic reconfigurable computing is not yet mature because of several unsolved problems. This work introduces the concept, architecture, and compilation techniques of dynamic reconfigurable computing. It also discusses the existing major challenges and points out its potential applications.

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Code Compression and Decompression for Coarse-Grain Reconfigurable Architectures

Cited by 11 publications

References 10 publications

Configuration Context Reduction for Coarse-Grained Reconfigurable Architecture

Configuration Context Reduction for Coarse-Grained Reconfigurable Architecture

Adaptive compression for instruction code of Coarse Grained Reconfigurable Architectures

Architecture, challenges and applications of dynamic reconfigurable computing

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