COD: alternative architectures for high speed packet switching

Performance characteristics of cascaded delay‐line node architectures in single‐path interconnection networks

“…two packets arrive at the input ports, the buffer space is fully occupied and all packets in the system are destined to the same output port), it is the oldest packet in the baseline architecture that is lost and the second oldest packet leaves the switch from the correct output port. However, in Reference [6] it was shown that this FIFO property does not hold for the TTC baseline architecture even if the delay line lengths at each module are equal and of one packet length ðd 0 ¼ d 1 ¼ 1Þ: This is because, in case of buffer overflow, the oldest packet is allowed to exit the baseline architecture and whereas the second oldest packet is lost. In turn order of arrivals is disrupted.…”

“…In Reference [6] it has been shown that by modifying the baseline architecture (i.e. changing delay line lengths) the packet loss rates can be minimized, which greatly reduces the required number of 2 Â 2 basic smart switches.…”

“…TC and TTC architectures, proposed by Cruz and Tsai, use the analogy of track changing trains [6]. The purpose of using the track changer is to make packets to move on their original tracks before exiting the module.…”

“…Based on the analytical models developed for the COD [6], SDL and logarithmic delay-line switch [10], an initial stand-alone comparison is carried out to justify the packet loss rate performance of each cascaded fibre delay line switch architecture. Figure 2a shows the packet loss rate against the traffic load for four optical switches.…”

“…Possible realizations of output and/or shared buffering are 2 Â 2 multistage feed forward delays ( Figure 1): cascaded optical delay-line (COD) [6], switched delay line [7][8][9] and logarithmic delay-line switch [10]. The common feature of these architectures is that all consist of n stages of delay line modules ðdÞ in cascade.…”