COBRA: A Framework for Evaluating Compositions of Hardware Branch Predictors

Zhao, Jerry; Gonzalez, Abraham; Amid, Alon; Karandikar, Sagar; Asanović, Krste

doi:10.1109/ispass51385.2021.00053

Cited by 1 publication

(2 citation statements)

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“…The prediction of a branch is not-taken if the dot-product sign is negative, and taken otherwise. To allow higher clock rates and to limit the latency to acceptable 3-4 cycles [40,41], we pipeline the prediction operation of SLBIU into 3 stages: 1 st stage performs the fully associative lookup, 2 nd stage extracts the model weights and LHR from the CAM, concatenates and selects history bits and flips weights signs, while 3 rd stage is dedicated to the adder-tree.…”

Section: Slbiu Functionalitymentioning

confidence: 99%

“…The 3 pipeline stages are balanced, with the critical path dictated by the adder tree (3 rd stage) due to the 16-bit operands in the short history configuration, and by the history selection (2 nd stage) in the long history configuration. Note that in 7nm same 3-cycle latency can also be retained under certain frequency requirements [40,41].…”

Section: Circuit-level Evaluationmentioning

confidence: 99%

See 1 more Smart Citation

Identifying and Exploiting Sparse Branch Correlations for Optimizing Branch Prediction

Zouzias¹,

Kalaitzidis²,

Berestizshevsky³

et al. 2022

Preprint

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Branch prediction is arguably one of the most important speculative mechanisms within a high-performance processor architecture. A common approach to improve branch prediction accuracy is to employ lengthy history records of previously seen branch directions to capture distant correlations between branches. The larger the history, the richer the information that the predictor can exploit for discovering predictive patterns. However, without appropriate filtering, such an approach may also heavily disorganize the predictor's internal mechanisms, leading to diminishing returns. This paper studies a fundamental control-flow property: the sparsity in the correlation between branches and recent history. First, we show that sparse branch correlations exist in standard applications and, more importantly, such correlations can be computed efficiently using sparse modeling methods. Second, we introduce a sparsity-aware branch prediction mechanism that can compactly encode and store sparse models to unlock essential performance opportunities. We evaluated our approach for various design parameters demonstrating MPKI improvements of up to 42% (2.3% on average) with 2KB of additional storage overhead. Our circuit-level evaluation of the design showed that it can operate within accepted branch prediction latencies, and under reasonable power and area limitations.

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Section: Slbiu Functionalitymentioning

confidence: 99%

Section: Circuit-level Evaluationmentioning

confidence: 99%